Dma Count Register (Dm0Cntrn, Dm1Cntrn) - Toshiba TMPR4937 Manual

8.4.9

DMA Count Register (DM0CNTRn, DM1CNTRn)

Offset Address: DMAC0 0xB018 (ch. 0) / 0xB058 (ch. 1) / 0xB098 (ch. 2) / 0xB0D8 (ch. 3)
63
47
31
Reserved
15
Bit Mnemonic Field Name
63:26 Reserved
25:0 DMCNTR Count
DMAC1 0xB818 (ch. 0) / 0xB858 (ch. 1) / 0xB898 (ch. 2) / 0xB8D8 (ch. 3)
Reserved
Reserved
26 25
DMCNTR[15:0]
R/W
⎯
Count Register (Default: undefined)
This register sets the byte count that is transferred by the DMA Channel
Register setting. The value is a 26-bit unsigned data that is decremented
only by the size of the data transferred during a single bus operation.
Refer to "8.3.7.1 Channel Register Settings During Single Address
Transfer" and "8.3.8.1 Channel Register Settings During Dual Address
Transfer" for more information.
Figure 8.4.9 DMA Count Register
8-38
Chapter 8 DMA Controller
DMCNTR[25:0]
R/W
⎯
Description
48
: Type
: Initial value
32
: Type
: Initial value
16
: Type
: Initial value
0
: Type
: Initial value
Read/Write
⎯
R/W