Power-On Sequence - Toshiba TMPR4937 Manual

Chapter 6 Clocks
6.3

Power-On Sequence

Vdd
MASTERCLK
RESET*
CGRESET*
PLL settling time
PLL1 output
CPUCLK
GBUSCLK
PCICLK
PCICLKIN (when PCICLK is fed back)
PLL settling time
PLL2 output
PCICLKO (clock for TX4937 PCI controller)
Figure 6.3.1 Power-On Sequence
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