Receive Fifo Register 0 (Sirfifo0) 0Xf320 (Ch. 0) Receive Fifo Register 1 (Sirfifo1) 0Xf420 (Ch. 1) - Toshiba TMPR4937 Manual

11.4.9 Receive FIFO Register 0 (SIRFIFO0) 0xF320 (Ch. 0)
Receive FIFO Register 1 (SIRFIFO1) 0xF420 (Ch. 1)
When using the DMA Controller to perform DMA transmission, set the following addresses in the
Destination Address Register (DMDARn) of the DMA Controller according to the Endian Mode bit
(DMCCRn.LE) setting of the DMA Controller.
•
Little Endian:
•
Big Endian:
31
15
Reserved
Bit Mnemonic Field Name
31:8 Reserved
7:0 RxD Reception Data
0xF320 (Ch.0), 0xF420 (Ch.1)
0xF323 (Ch.0), 0xF423 (Ch.1)
Reserved
8 7
Receive Data
This field reads reception data from the Receive FIFO.
Reading this register updates the Reception Data Status.
Figure 11.4.9 Receive FIFO Register
11-24
Chapter 11 Serial I/O Port
RxD
R
Undefined
Description
16
: Type
: Initial value
0
: Type
: Initial value
Read/Write
⎯
R