Toshiba TMPR4937 Manual page 524

64-bit tx system risc
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Table 22.1.1 Pin Cross Reference by Pin Number (1/2)
Pin
Pin
Num-
Num-
Pin Name
ber
ber
A1
PIO[1]
B17
A2
PIO[0]
B18
A3
SWE*
B19
A4
CE[7]*
B20
A5
CE[5]*
B21
A6
CE[4]*
B22
A7
DMAACK[2]
B23
A8
DMAACK[1]
B24
A9
BWE[0]*
B25
A10
BWE[1]*
B26
A11
EEPROM_DI
C1
A12
EEPROM_DO
C2
A13
VSS
C3
A14
EEPROM_SK
C4
A15
EEPROM_CS
C5
A16
PCST[3]
C6
A17
PCST[0]
C7
A18
PCIAD[2]
C8
A19
PCIAD[5]
C9
A20
C_BE[0]
C10
A21
PCIAD[11]
C11
A22
PCIAD[15]
C12
A23
VSS
C13
A24
VddIO
C14
A25
IRDY*
C15
A26
C_BE[2]
C16
B1
PIO[3]
C17
B2
PIO[2]
C18
B3
BUSSPRT*
C19
B4
CE[6]*
C20
B5
VddIO
C21
B6
CE[3]*
C22
B7
DMAACK[3]
C23
B8
DMAREQ[2]
C24
B9
DMAREQ[1]
C25
B10
BWE[2]*
C26
B11
TCK
D1
B12
DCLK
D2
B13
TDO
D3
B14
PCST[8]
D4
B15
PCST[5]
D5
B16
PCST[2]
D6
Chapter 22 Pinout and Package Information
Pin
Num-
Pin Name
Pin Name
ber
PCIAD[0]
D7
CE[0]*
PCIAD[3]
D8
VddIN
PCIAD[6]
D9
VSS
PCIAD[8]
D10
VddIN
PCIAD[12]
D11
DMAACK[0]
C_BE[1]
D12
VddIO
PERR*
D13
TPC[2]
STOP*
D14
VddIO
FRAME*
D15
VddIN
VSS
D16
VddIO
PIO[5]
D17
VddIN
PIO[4]
D18
PCIAD[4]
VddIO
D19
VddIO
ACK*
D20
M66EN
ACE*
D21
VddIO
CE[2]*
D22
SERR*
CE[1]*
D23
VddIN
DMAREQ[3]
D24
TRDY*
VddIO
D25
VddIO
BWE[3]*
D26
PCIAD[18]
TDI
E1
TCLK
TMS
E2
TIMER[0]
TPC[3]
E3
TIMER[1]
PCST[7]
E4
VddIO
PCST[4]
E5
VSS
PCST[1]
E6
SDIN[1]
PCIAD[1]
E7
VddIO
VddIO
E8
VSS
PCIAD[7]
E9
DMADONE*
PCIAD[9]
E10
VSS
PCIAD[13]
E11
DMAREQ[0]
PAR
E12
VSS
LOCK*
E13
TPC[1]
DEVSEL*
E14
PCST[6]
PCIAD[17]
E15
VSS
PCIAD[16]
E16
TRST*
PIO[7]
E17
VSS
VSS
E18
VSS
PIO[6]
E19
VSS
VddIN
E20
PCIAD[10]
BYPASSPLL*
E21
PCIAD[14]
VSS
E22
VSS
22-4
Pin
Pin
Num-
Num-
Pin Name
ber
ber
E23
PCIAD[22]
J25
E24
PCIAD[21]
J26
E25
PCIAD[20]
K1
E26
PCIAD[19]
K2
F1
INT[2]
K3
F2
INT[1]
K4
F3
INT[0]
K5
F4
NMI*
K22
F5
VddIN
K23
F22
VddIO
K24
F23
C_BE[3]
K25
F24
ID_SEL
K26
F25
VddIO
L1
F26
PCIAD[23]
L2
G1
INT[5]
L3
G2
INT[4]
L4
G3
INT[3]
L5
G4
RXD[0]
L22
G5
VddIN
L23
G22
PCIAD[28]
L24
G23
PCIAD[27]
L25
G24
PCIAD[26]
L26
G25
PCIAD[25]
M1
G26
PCIAD[24]
M2
H1
TXD[0]
M3
H2
RTS[0]*
M4
H3
CTS[0]*
M5
H4
VddIO
M22
H5
VSS
M23
H22
VSS
M24
H23
VddIN
M25
H24
PCIAD[29]
M26
H25
VddIO
N1
H26
PCICLK[0]
N2
J1
SCLK
N3
J2
TXD[1]
N4
J3
RTS[1]*
N5
J4
CTS[1]*
N22
J5
RXD[1]
N23
J22
PCIAD[31]
N24
J23
VSS
N25
J24
PCIAD[30]
N26
Pin Name
GNT[0]*
PCICLK[1]
RESET*
TEST[0]*
HALTDOZE
VddIN
VSS
VSS
VddIN
GNT[1]*
REQ[0]*
PCICLK[2]
SYSCLK
TEST[4]*
TEST[3]*
TEST[2]*
TEST[1]*
REQ[1]*
VSS
REQ[2]*
GNT[2]*
PCICLK[3]
OE*
WDRST*
VddIO
VddIN
VSS
VSS
VddIO
REQ[3]*
GNT[3]*
PCICLK[4]
DATA[1]
DATA[32]
DATA[0]
VSS
VddIO
PME*
VddIO
VSS
DATA[63]
PCICLK[5]

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