Toshiba TMPR4937 Manual page 92

Bit Mnemonic Field Name
SIO0 Clock
17 SIO0CKD
Disable
SIO1 Clock
16 SIO1CKD
Disable
⎯
15:11 Reserved
10 DMA1RST DMAC1 Reset
9 ACLRST ACLC Reset
8 PIORST PIO Reset
7 DMARST DMAC Reset
6 PCICRST PCIC Reset
⎯ ⎯
5
4 TM0RST TMR0 Reset
3 TM1RST TMR1 Reset
2 TM2RST TMR2 Reset
1 SIO0RST SIO0 Reset
0 SIO1RST SIO1 Reset
Chapter 5 Configuration Registers
Description
Controls clock pulses for the SIO0 controller.
0 = Supply clock pulses.
1 = Do not supply clock pulses.
Controls clock pulses for the SIO1 controller.
0 = Supply clock pulses.
1 = Do not supply clock pulses.
⎯
Resets the DMAC controller 1.
0 = Normal state
1 = Reset
Resets the AC-link controller.
0 = Normal state
1 = Reset
Note: Reset the AC-link controller when it is not asserting the
interrupt and DMA request.
Resets the parallel IO controller.
0 = Normal state
1 = Reset
Resets the DMA controller.
0 = Normal state
1 = Reset
Resets the PCI controller.
0 = Normal state
1 = Reset
Always set this bit to 1.
Resets the TMR0 controller.
0 = Normal state
1 = Reset
Resets the TMR1 controller.
0 = Normal state
1 = Reset
Resets the TMR2 controller.
0 = Normal state
1 = Reset
Resets the SIO0 controller.
0 = Normal state
1 = Reset
Resets the SIO1 controller.
0 = Normal state
1 = Reset
Figure 5.2.5 Clock Control Register (2/2)
5-12
Initial Value Read/Write
0 R/W
0 R/W
⎯ ⎯
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
1 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W