Block Diagram - Toshiba TMPR4937 Manual

9.2

Block Diagram

G-Bus
I/F Signal
Interface
G-Bus
I/FSignal
G-Bus
SDRAMC
Channel 0 – 7
Control Register
Timing Register
G-Bus
Command/Load
Control
Register
Refresh Counter
ECC
Control Signal
ECC
Control Signal
ECC
Figure 9.2.1 Block Diagram of SDRAMC
9-2
Chapter 9 SDRAM Controller
SDCS [3 : 0] *
CKE
WE*
RAS*
Control
Circuit CAS*
DQM [7 : 0]
EBIF
Control Signal
ADDR [19 : 5]
DATA [63 : 0]
EBIF
CB [7 : 0]
CG
SDCLK[3:0]