Toshiba TMPR4937 Manual page 548

64-bit tx system risc
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Page
Rev 1.1 Manual
Figure 7.3.13 Ready Input Timing (Read Cycle)
7-18
Figure 7.3.13 Ready Input Timing (Read Cycle)
7-18
Figure 7.3.14 Ready Input Timing (Write Cycle)
7-19
Figure 7.3.14 Ready Input Timing (Write Cycle)
7-19
Start Ready
Figure 7.5.3
Double-word Single Write (PWT: WT=1,
7-27
SHWT=0, Normal, 32-bit Bus)
2 clock
Acknowledge Ready
Start Ready
Acknowledge Re
Check
3 clock
Acknowledge Ready
Acknowledge Read
Check
4
TMPR4937 Revision History
Changes and Additions to Rev 1.1
Acknowledge Ready
Start Ready
Check
4
Acknowledge Ready
Start Ready
Check
Figure 7.5.3 Double-word Single Write (PWT: WT=0,
SHWT=0, Normal, 32-bit Bus)
2 clocks
Latch D
E
Acknowledge Re
3 clocks
4 clocks
Acknowledge
Ready

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