Toshiba TMPR4937 Manual page 430

Bit Mnemonic Field Name
REGACCRDY ACREGACC
4
Ready
⎯
3:2 Reserved
1 CODEC1RDY CODEC1 Ready
0 CODEC0RDY CODEC0 Ready
Description
REGACCRDY: ACREGACC Ready
R 1: Indicates that the ACREGACC register is ready to get the value
(in case the previous operation was a read access) and to
initiate another R/W access to an AC'97 register.
The result of reading or writing to the ACREGACC register before
the completion notification is undefined.
This bit is cleared if "1" is written to it.
W1C This bit automatically becomes '0' when the ACREGACC register
is written.
CODEC1RDY: CODEC1 Ready
R 1: Indicates that the CODEC Ready bit of SDIN1 Slot0 is set.
CODEC0RDY: CODEC0 Ready
R 1: Indicates that the CODEC Ready bit of SDIN0 Slot0 is set.
Figure 14.4.4 ACINTSTS Register (2/2)
14-24
Chapter 14 AC-link Controller
Read/Write
R/W1C
⎯
R
R