Dma Destination Address Increment Register (Dm0Dairn, Dm1Dairn) - Toshiba TMPR4937 Manual

8.4.8

DMA Destination Address Increment Register (DM0DAIRn, DM1DAIRn)

Offset Address: DMAC0 0xB028 (ch. 0) / 0xB068 (ch. 1) / 0xB0A8 (ch. 2) / 0xB0E8 (ch. 3)
63
47
31
Reserved
15
Bit Mnemonic Field Name
63:24 Reserved
23:0 DADINC Destination
Address
Increment
Figure 8.4.8 DMA Destination Address Increment Register
DMAC1 0xB828 (ch. 0) / 0xB868 (ch. 1) / 0xB8A8 (ch. 2) / 0xB8E8 (ch. 3)
Reserved
Reserved
24 23
DADINC[15:0]
R/W
⎯
Destination Address Increment (Default: undefined)
This field sets the increase/decrease value of the DMA Destination
Address Register (DMDARn). This value is a 24-bit two's complement and
indicates a byte count.
Refer to "8.3.8.1 Channel Register Settings During Dual Address Transfer"
for more information.
8-37
Chapter 8 DMA Controller
DADINC[23:16]
R/W
⎯
Description
48
: Type
: Initial value
32
: Type
: Initial value
16
: Type
: Initial value
0
: Type
: Initial value
Read/Write
⎯
R/W