Toshiba TMPR4937 Manual page 243

64-bit tx system risc
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Chapter 9 SDRAM Controller
SDCLK
SDCS*
ADDR [19:5]
7fff
0000
RAS*
CAS*
WE*
CKE
DQM [7:0]
ff
00
ff
DATA [63:0]
CB [7:0]
ACK*/READY*
= 3, t
= 3, t
= 1, 64-bit Bus)
Figure 9.5.2 Single Read (t
RCD
CASL
DA
9-27

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