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14.4.5
ACLC Interrupt Masked Status Register
Every bit in this register is configured as follows:
ACINTMSTS = ACINTSTS & ACINTEN
Bit placement is the same as for the ACINTSTS register. The logical OR of all bits in this register is
used as ACLC interrupt request to the interrupt controller.
14.4.6
ACLC Interrupt Enable Register
Interrupt request enable (R/W1S). Bit placement is the same as for the ACINTSTS register. Its
initial value is all '0'. When a value is written to this register, the bit in the position where "1" was
written is set to "1."
14.4.7
ACLC Interrupt Disable Register
Interrupt request enable clear (W1C). Bit placement is the same as for the ACINTSTS register.
When a value is written to this register, the ACINTEN register bit in the position where a "1" was
written is cleared to "0."
Chapter 14 AC-link Controller
0xF714
0xF718
0xF71C
14-25
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