Dma Source Address Increment Register (Dm0Sairn, Dm1Sairn) - Toshiba TMPR4937 Manual

8.4.7

DMA Source Address Increment Register (DM0SAIRn, DM1SAIRn)

Offset Address: DMAC0 0xB020 (ch. 0) / 0xB060 (ch. 1) / 0xB0A0 (ch. 2) / 0xB0E0 (ch. 3)
63
47
31
Reserved
15
Bit Mnemonic Field Name
63:24 Reserved
23:0 SADINC Source Address
Increment
DMAC1 0xB820 (ch. 0) / 0xB860 (ch. 1) / 0xB8A0 (ch. 2) / 0xB8E0 (ch. 3)
Reserved
Reserved
24
SADINC[15:0]
R/W
Source Address Increment (Default: undefined)
This field sets the increase/decrease value of the DMA Source Address
Register (DMSARn). This value is a 24-bit two's complement and indicates
a byte count.
Refer to "8.3.7.1 Channel Register Settings During Single Address
Transfer" and "8.3.8.1 Channel Register Settings During Dual Address
Transfer" for more information.
Figure 8.4.7 DMA Source Address Increment Register
8-36
Chapter 8 DMA Controller
23
SADINC[23:16]
R/W
⎯
⎯
Description
48
: Type
: Initial value
32
: Type
: Initial value
16
: Type
: Initial value
0
: Type
: Initial value
Read/Write
⎯
R/W