Toshiba TMPR4937 Manual page 425

Bit Mnemonic Field Name
⎯
7:6 Reserved
Clear CODEC
5 RDYCLR
Ready Bit
MIC Selection
4 MICSEL
Assert Warm
3 WRESET
Reset
Enable Wake-up
2 WAKEUP
Enable AC-link
1 LOWPWR
low-power mode
Enable AC-link
0 ENLINK
Description
RDYCLR: Clear CODEC Ready Bit
W1C 0: No effect
1: Clear CODEC[1:0] ready bits
[Note: This bit should only be written to reevaluate the CODEC
ready status after power-down command is sent to CODEC.]
MICSEL: MIC Selection.
R 0: Indicates that PCM L&R (Slot 3&4) is selected for audio reception.
1: Indicates that MIC (Slot 6) is selected for audio reception.
W1S 0: No effect
1: Selects MIC (Slot 6) for audio reception.
WRESET: Assert Warm Reset.
R 0: Indicates that warm reset is not asserted.
1: Indicates that warm reset is asserted.
W1S 0: No effect
1: Asserts warm reset.
[Note 1: Do not assert warm reset during normal operation.]
[Note 2: The software must guarantee the warm reset assertion
time meets the AC'97 specification (1.0 µs or more).]
WAKEUP: Enable Wake-up.
R 0: Indicates that wake-up from low-power mode is disabled.
1: Indicates that wake-up from low-power mode is enabled. While
any SDIN signal is driven high, ACLC asserts ACLCPME interrupt
request to the interrupt controller.
W1S 0: No effect
1: Enables wake-up from low-power mode.
[Note: Do not enable wake-up during normal operation.]
LOWPWR: Enable AC-link Low-power Mode.
R 0: SYNC and SDOUT signals are not forced to low.
1: SYNC and SDOUT signals are forced to low.
W1S 0: No effect
1: Forces SYNC and SDOUT signals low.
[Note: Do not enable AC-link low-power mode during normal
operation.]
ENLINK: Enable AC-link.
R 0: Indicates that the ACRESET* signal to AC-link is asserted.
1: Indicates that the ACRESET* signal to AC-link is not asserted.
W1S 0: No effect
1: Deasserts the ACRESET* signal to AC-link
[Note: The software must guarantee the ACRESET* signal
assertion time meets the AC'97 specification (1.0 µs or
more).]
Figure 14.4.1 ACCTLEN Register (3/3)
14-19
Chapter 14 AC-link Controller
Read/Write
⎯
W1S
R/W1S
R/W1S
R/W1S
R/W1S
R/W1S