Supported Pci Bus Commands - Toshiba TMPR4937 Manual

10.3.3

Supported PCI Bus Commands

Table 10.3.1 shows the PCI Bus commands that the PCI Controller supports.
C/BE Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Note: The byte enable signals are asserted as necessary during memory read and memory
write cycles using I/O Read, I/O Write and Single Access commands. During burst
memory reads, four byte enable signals are asserted.
√ : Supported when in both the Host mode and the Satellite mode
Key:
† : Supported only when in the Host mode
‡ : Supported only when in the Satellite mode
— : Not supported
•
I/O Read, I/O Write, Memory Read, Memory Write
This command executes Read/Write access to the address mapped on the G-Bus and PCI Bus.
•
Memory Read Multiple, Memory Read Line
The Memory Read Multiple command is issued if all of the following conditions are met when
the Initiator function is operating and Burst Read access is issued from the G-Bus to the PCI Bus.
(1) A value other than "0" is set to the Cache Line Size Field (PCICFG1.CLS) of the PCI
Configuration 1 Register.
(2) The Read data word count is equal to or less than the value set in the Cache Line Size Field.
Also, the Read Memory Line command is issued when all of the following conditions are met.
(1) A value other than "0" is set to the Cache Line Size Field (PCICFG1.CLS) of the PCI
Configuration 1 Register.
(2) The Read data word count is equal to or less than the value set in the Cache Line Size Field.
Table 10.3.1 Supported PCI Bus Commands
PCI Command
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
(Reserved)
(Reserved)
Memory Read
Memory Write
(Reserved)
(Reserved)
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write and Invalidate
10-6
Chapter 10 PCI Controller
As Initiator As Target
⎯
†
⎯
†
√ √
√ √
⎯ ⎯
⎯ ⎯
√ √
√ √
⎯ ⎯
⎯ ⎯
† ‡
† ‡
√ √
√ √
√ √
√ √