Features Of The Tx49/H3 Core; Features Of Tx4937 Peripheral Functions - Toshiba TMPR4937 Manual

1.2.1

Features of the TX49/H3 core

The TX49/H3 core is a high-performance, low power consumption 64-bit RISC CPU core that
Toshiba developed.
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64-bit operation
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32 64-bit integer general-purpose registers
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64 GB physical address space
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Optimized 5-stage pipeline
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Instruction Set
Upwards compatible MIPS III ISA
Added 3-operand multiply instruction, MAC (multiply accumulate) instruction, and PREF (pre-
fetch) instruction
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Supports 32 KB Instruction cache, 32 KB Data cache, 4-way set associative, and the lock function
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MMU (Memory Management Unit)
48 double entry (odd/even) joint TLB
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On-chip IEEE754-compatible single-precision and double-precision FPU
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4-stage write buffer mounted
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Debugging Support Unit: EJTAG
1.2.2

Features of TX4937 peripheral functions

(1) External Bus Controller (EBUSC)
The External Bus Controller generates the signals necessary to control external memory and
external I/O devices.
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Has 8-channel Chip Select signal, can control up to 8 external devices
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Supports access of ROM (mask ROM, page mode ROM, EPROM, EEPROM), SRAM, Flash
ROM, and I/O devices
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Can set data bus width to 32 bits, 16 bits, or 8 bits for each channel
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System clock for External Bus Controller (SYSCLK) frequency is up to 133 MHz (For
relationship between CPU clock and this system clock, see Section 6.1)
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Can select full speed, 1/2 speed, 1/3 speed , or 1/4 speed for each channel
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Can set timing for each channel
Can set up and set the Hold interval of the Address, Chip Enable, Write Enable, and Output
Enable signals
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Supports access of devices with a 32-bit wide data bus in memory sizes from 1 MB to 1 GB.
Supports access of devices with a 16-bit wide data bus in memory sizes from 1 MB to 512
MB. Supports access of devices with an 8-bit wide data bus in memory sizes from 1 MB to
256 MB.
Chapter 1 Overview and Features
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