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It is possible to set each space to valid/invalid, pre-fetch Read to valid/invalid, or to perform Word
Swap (see10.3.7). Table 10.3.5 shows the settings registers for these properties.
When pre-fetch Reads are set to valid, data transfer is performed on the G-Bus according to the size
set by the Target Pre-fetch Read Burst Length Field (P2GCFG.TPRBL) of the P2G Configuration
Register during a PCI target Read transaction. This is performed using accesses to resources that will
not be affected even if a pre-read such as memory is performed. Also, PCI Burst Reads to memory
spaces that were set to I/O space and pre-fetch disable are not supported.
Note: Always use PCI single reads. Don't use burst reads.
Table 10.3.5 Target Access Space Properties Register
PCICCFG.TCAR & MemEnable &
Memory Space 0
P2GM0GBASE.P2GM0EN
PCICCFG.TCAR & MemEnable &
Memory Space 1
P2GM1GBASE.P2GM1EN
PCICCFG.TCAR & MemEnable &
Memory Space 2
P2GM2GBASE.P2GM2EN
PCICCFG.TCAR & IOEnable &
I/O Space
P2GIOGBASE.P2GIOEN
MemEnable:
Host mode:
Satellite mode: Command Register Memory Space bit
IOEnable:
Host mode:
Satellite mode: Command Register I/O Space bit
10.3.6
Post Write Function
The Post Write function improves system performance by completing the original bus Write
transaction without waiting for the other bus to complete its transaction when the first bus issues a Write
transaction. Initiator Write can Post Write a maximum of four Write transactions, and Target Write can
Post Write a maximum of nine Write transactions.
Due to compatibility issues with old PC software in the PCI specifications, performing Post Writes
with Initiator Configuration Write and Target I/O Write is not recognized. However, the TX4937 PCI
Controller can even perform Post Writes to these functions. In order to guarantee that these Writes are
completed by the target device, please execute Reads to the device that performed the Write, then either
refer to the read value (so the TX49/H3 core can support non-blocking load) or execute the SYNC
instruction.
10.3.7
Endian Switching Function
The TX4937 supports both the Little Endian mode and the Bit Endian mode. On the other hand, the
PCI Bus is only defined in Little Endian logic. Therefore, when the TX4937 is in the Big Endian mode,
either the software or the hardware must perform some kind of conversion when exchanging data larger
than 2 B in size with the PCI Bus.
The PCI Controller can specify the endian switching function that reverses the byte arrangement of
the DWORD (32-bit) data for each access window.
Enable
Pre-fetch (Initial State)
P2GCFG.MEM0PD (valid)
P2GCFG.MEM1PD (valid)
P2GCFG.MEM2PD (invalid)
Always invalid
PCI State Command Register Memory Space bit (PCISTATUS.MEMSP)
PCI State Command Register I/O Space bit (PCISTATUS.IOSP)
10-12
Chapter 10 PCI Controller
Word Swap
P2GM0GBASE.BSWAP
P2GM1GBASE.BSWAP
P2GM2GBASE.BSWAP
P2GIOGBASE.BSWAP
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