P2G Memory Space 0 G-Bus Base Address Register (P2Gm0Gbase) 0Xd180 - Toshiba TMPR4937 Manual

10.4.46 P2G Memory Space 0 G-Bus Base Address Register (P2GM0GBASE)
63
47
Reserved
31 29 28
BA[31:29]
R/W
0x00
15
Bit Mnemonic Field Name
63:39 Reserved
38 P2GM0EN Memory Space 0
Enable
37 BSWAP Byte Swap
36 EXFER Endian Transfer
35:29 BA[35:29] Base Address
28:0 Reserved
Figure 10.4.44 P2G Memory Space 0 G-Bus Base Address Register
Reserved
39 38
P2GM0EN
R/W
0x0
Reserved
Reserved
Description
Target Memory Space 0 Enable (Default: 0x0) Controls whether Memory
Space 0 for target access is valid or invalid.
When this bit is set to invalid, Writes to the Memory Space 0 Lower Base
Address Register or the Memory Space 0 Upper Base Address Register of
the PCI Configuration Register become invalid. Also, "0" is returned to
Reads as a response.
1: Validates Memory Space 0 for target access.
0: Invalidates Memory Space 0 for target access.
Byte Swap Disable
(Default: Little Endian Mode: 0x1; Big Endian Mode: 0x0) Sets the byte
swapping of Memory Space 0 for target access..
1: Do not perform byte swapping.
0: Perform byte swapping.
Please use the default state in most situations. If this bit is changed to "1"
when in the Big Endian Mode, the byte order of transfer to Memory Space
0 through DWORD (32-bit) access will not change.
Endian Transfer
(Default: Little Endian Mode: 0x0; Big Endian Mode: 0x1) Sets the Endian
Transfer of Memory Space 0 for target access.
1: Performs Endian Transfer.
0: Does not perform Endian Transfer.
Please use the default state.
Base Address 0 (Default: 0x000)
Sets the G-Bus base bus address of Memory Space 0 for target access.
Can set the base address in 512-MB units.
10-77
Chapter 10 PCI Controller
37 36 35
EXFER BA[35:32]
BSWAP
R/W R/W R/W
0x0
0x0/0x1 0x1/0x0
0xD180
48
: Type
: Initial value
32
: Type
: Initial value
16
: Type
: Initial value
0
: Type
: Initial value
Read/Write
⎯
R/W
R/W
R/W
R/W
⎯