Toshiba TMPR4937 Manual page 49

(2) Direct Memory Access Controllers (DMAC)
The TX4937 has two DMA Controllers for invoking DMA transfer with memory and I/O
devices. Each DMA Controller has 4 built-in DMA Channels.
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Can set internal/external DMA requests
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Supports as internal DMA requests DMA with the on-chip Serial I/O Controller or AC-link
Controller
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Supports as external I/O DMA transfer modes using external DMA requests Single Address
transfer (Fly-by DMA) and Dual Address transfer
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Supports transfer between external devices with a data bus width of 32 bits, 16 bits or 8 bits
and memory
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Supports memory-memory copy mode that has no address boundary constraints
Can perform Burst transfer of up to 8 double words in a single read or write operation
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Supports the Memory Fill mode that writes double-word data to the memory region
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Supports Chain DMA transfer
(3) SDRAM Controller (SDRAMC)
The SDRAM Controller generates the control signals required for the SDRAM interface. By
having 4 on-chip channels and supporting a variety of memory configurations, the SDRAM
Controller can support memory sizes of up to 4 GB (1 GB/channel).
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Memory clock (SDCLK) frequencies from 50 MHz to 133 MHz (For relationship between
CPU clock and memory clock, see Section 6.1)
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4 sets of independent memory channels
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Supports 2-bank or 4-bank 16 MB, 64 MB, 128 MB, 256 MB, or 512 MB SDRAM
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Can used Registered DIMM
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Supports ECC or parity generation/check functions
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Can select either 32-bit or 64-bit data bus width for each channel
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Can set SDRAM timing for each channel
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Supports TX49/H3 core critical word first access
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Low power consumption mode: can select Self-refresh or Pre-charge power down
(4) PCI Controller (PCIC)
The TX4937 has an on-chip PCI Controller that is compliant with PCI Local Bus Specification
Revision 2.2.
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PCI Local Bus Specification Revision 2.2 compliant
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32-bit PCI interface with maximum PCI Bus clock frequency of 66 MHz
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Supports both the Target and Initiator functions
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Can change the address mapping between the internal bus and PCI Bus
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Has an on-chip PCI Bus arbiter and can connect up to 4 External Bus Masters
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Has a function mounted for booting the TX4937 from memory on the PCI Bus
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Has an on-chip 1-channel PCI Controller-dedicated DMA Controller (PDMAC)
Chapter 1 Overview and Features
1-3