Interrupt Request Flag Register 0 (Irflag0) 0Xf510; Interrupt Request Flag Register 1 (Irflag1) 0Xf514 - Toshiba TMPR4937 Manual

15.4.17 Interrupt Request Flag Register 1 (IRFLAG1)
31
15 14 13 12
PF1 PF1 PF1 PF1
[15] [14] [13] [12]
Bit Mnemonic Field Name
⎯
31:16
15:0 PF1 [15:0] Flag 1
Reserved
11 10 9 8
PF1 PF1 PF1 PF1
[11] [10] [9] [8]
R/W
0x0000
⎯
Reserved
Interrupt Request Flag 1 [15:0] (Default: 0x0000)
Changes made to this register are reflected in Flag Register 0 also since
they are the same registers.
Writes to Flag Register 1 operate as follows:
Write
Write from the TX49/H3 core
1: Set the flag bit
0: No change
Write from other devices (DMAC, PCIC)
1: Clear the flag bit
0: No change
Read: Read the flag bit
Figure 15.4.17 Interrupt Request Flag Register 1
15-40
Chapter 15 Interrupt Controller
0xF514
7 6 5 4
PF1 PF1 PF1 PF1 PF1
[7] [6] [5] [4] [3]
Explanation
16
: Type
: Default
3 2 1 0
PF1 PF1 PF1
[2] [1] [0]
: Type
: Default
Read/Write
⎯
R/W