Block Diagram - Toshiba TMPR4937 Manual

8.2

Block Diagram

DMAC0
DMA
Control 0
Block
G-Bus
I/F
FIFO
(8 Double
Words)
DMA Channel Arbiter
DMA0
Channel 0
DM0MCR
DM0MFDR
DMA0
Channel 1
DMA0
Channel 2
DMA0
Channel 3
Figure 8.2.1 DMA0 Controller Block Diagram
8-2
Chapter 8 DMA Controller
DMAREQ[0]
DM0CHAR0
DREQ0
DM0SAR0
DMAACK[0]
DM0DAR0
DACK0
DM0CNTR0
DM0SAIR0
DM0DAIR0
DM0CCR0
PCFG.DMASEL0
DM0CSR0
DMAREQ[1]
DM0CHAR1
DREQ1
DM0SAR1
DMAACK[1]
DM0DAR1
DMCK1
DM0CNTR1
DM0SAIR1
DM0DAIR1
DM0CCR1
PCFG.DMASEL1
DM0CSR1
DMAREQ[2]
DM0CHAR2
DREQ2
DM0SAR2
DMAACK[2]
DM0DAR2
DACK2
DM0CNTR2
DM0SAIR2
DM0DAIR2
DM0CCR2
PCFG.DMASEL2
DM0CSR2
DMAREQ[3]
DM0CHAR3
DREQ3
DM0SAR3
DMAACK[3]
DM0DAR3
DMCK3
DM0CNTR3
DM0SAIR3
DM0DAIR3
DM0CCR3
PCFG.DMASEL3
DM0CSR3
DMADONE*
External
Pins
Internal I/O
(Receive SIO ch1)
External
Pins
Internal I/O
(Transfer SIO ch1)
External
Pins
Internal I/O
(Receiver SIO ch0)
External
Pins
Internal I/O
(Transfer SIO ch0)
External
Pins