Toshiba TMPR4937 Manual page 180

Offset Address Bit Width
0xB800 64
0xB808 64
0xB810 64
0xB818 64
0xB820 64
0xB828 64
0xB830 64
0xB838 64
0xB840 64
0xB848 64
0xB850 64
0xB858 64
0xB860 64
0xB868 64
0xB870 64
0xB878 64
0xB880 64
0xB888 64
0xB890 64
0xB898 64
0xB8A0 64
0xB8A8 64
0xB8B0 64
0xB8B8 64
0xB8C0 64
0xB8C8 64
0xB8D0 64
0xB8D8 64
0xB8E0 64
0xB8E8 64
0xB8F0 64
0xB8F8 64
0xB948 64
0xB950 64
Table 8.4.2 DMA Controller 1 Registers
Mnemonic
DM1CHAR0 DMA Chain Address Register 0
DM1SAR0 DMA Source Address Register 0
DM1DAR0 DMA Destination Address Register 0
DM1CNTR0 DMA Count Register 0
DM1SAIR0 DMA Source Address Increment Register 0
DM1DAIR0 DMA Destination Address Increment Register 0
DM1CCR0 DMA Channel Control Register 0
DM1CSR0 DMA Channel Status Register 0
DM1CHAR1 DMA Chain Address Register 1
DM1SAR1 DMA Source Address Register 1
DM1DAR1 DMA Destination Address Register 1
DM1CNTR1 DMA Count Register 1
DM1SAIR1 DMA Source Address Increment Register 1
DM1DAIR1 DMA Destination Address Increment Register 1
DM1CCR1 DMA Channel Control Register 1
DM1CSR1 DMA Channel Status Register 1
DM1CHAR2 DMA Chain Address Register 2
DM1SAR2 DMA Source Address Register 2
DM1DAR2 DMA Destination Address Register 2
DM1CNTR2 DMA Count Register 2
DM1SAIR2 DMA Source Address Increment Register 2
DM1DAIR2 DMA Destination Address Increment Register 2
DM1CCR2 DMA Channel Control Register 2
DM1CSR2 DMA Channel Status Register 2
DM1CHAR3 DMA Chain Address Register 3
DM1SAR3 DMA Source Address Register 3
DM1DAR3 DMA Destination Address Register 3
DM1CNTR3 DMA Count Register 3
DM1SAIR3 DMA Source Address Increment Register 3
DM1DAIR3 DMA Destination Address Increment Register 3
DM1CCR3 DMA Channel Control Register 3
DM1CSR3 DMA Channel Status Register 3
DM1MFDR DMA Memory Fill Data Register
DM1MCR DMA Master Control Register
8-24
Chapter 8 DMA Controller
Register Name