Pci Status Interrupt Mask Register (Pcimask) 0Xd08C - Toshiba TMPR4937 Manual

10.4.18 PCI Status Interrupt Mask Register (PCIMASK) 0xD08C

31
15 14 13 12
DPEIE SSEIE RMAIE RTAIE STAIE
R/W R/W R/W R/W
0x0 0x0 0x0 0x0
Bit Mnemonic Field Name
31:16 Reserved
15 DPEIE Detected Parity
Error Interrupt
Enable
14 SSEIE Signaled System
Error Interrupt
Enable
13 RMAIE Received Master
Abort Interrupt
Enable
12 RTAIE Received Target
Abort Interrupt
Enable
11 STAIE Signaled Target
Abort Interrupt
Enable
13 RMA Received Master
Abort
12 RTA Received Target
Abort
Signaled Target
11 STA
Abort
10:9 Reseved
8 MDPEIE Master Data
Parity Detected
Interrupt Enable
7:0 Reserved
Reserved
11 10 9 8
Reserved
MDPEIE
R/W R/W
0x0 0x0
Detected Parity Error Interrupt Enable (Default: 0x0)
Generates an interrupt when a parity error is detected.
Usually, this interrupt is masked and a Master Data Parity error signals the
error to the system.
1: Generates an interrupt.
0: Does not generate an interrupt.
Signaled System Error Interrupt Enable (Default: 0x0)
Generates an interrupt when a system error is signaled.
1: Generates an interrupt.
0: Does not generate an interrupt.
Received Master Abort Interrupt Enable (Default: 0x0)
Generates an interrupt when a Master Abort is received.
1: Generates an interrupt.
0: Does not generate an interrupt.
Received Target Abort Interrupt Enable (Default: 0x0)
Generates an interrupt when a Target Abort is received.
1: Generates an interrupt.
0: Does not generate an interrupt.
Signaled Target Abort Interrupt Enable (Default: 0x0)
Generates an interrupt when a Target Abort is signaled.
1: Generates an interrupt.
0: Does not generate an interrupt.
Received Master Abort (Default: 0x0)
This is a shadow register of the PCISTATUS.RMA bit.
Received Target Abort (Default: 0x0)
This is a shadow register of the PCISTATUS.RTA bit.
Signaled Target Abort (Default: 0x0)
This is a shadow register of the PCISTATUS.STA bit.
Master Data Parity Detected Interrupt Enable (Default: 0x0)
Generates an interrupt when data parity is detected.
1: Generates an interrupt.
0: Does not generate an interrupt.
Figure 10.4.16 PCI Status Interrupt Mask Register
10-43
Chapter 10 PCI Controller
7
Reserved
Description
16
: Type
: Initial value
0
: Type
: Initial value
Read/Write
⎯
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
⎯
R/W
⎯