G2P Configuration Data Register (G2Pcfgdata) 0Xd1A4 - Toshiba TMPR4937 Manual

10.4.51 G2P Configuration Data Register (G2PCFGDATA)
This is the only register that supports Byte access and 16-bit Word access. The upper address bit of
the PCI Configuration Space is specified by the G2P Configuration Address Register (G2PCFGADRS).
The lower two bits of the address are specified by the lower two bits of the offset address in this register
as shown in Figure 10.4.2.
The operation of any access to this register is undefined when the PCI Controller is in the Satellite
mode.
Access Size
32-bit
16-bit
8-bit
31
15
Bits Mnemonic Field Name
31:0 ICD Initiator
Configuration
Data
Table 10.4.2 PCI Configuration Space Access Address
Configuration Space
Address [1:0]
00
00
10
00
01
10
11
ICD
R/W
⎯
ICD
R/W
⎯
Initiator Configuration Data Register (Default--)
This is a data port that is used when performing initiator PCI configuration
access. PCI configuration Read or Write transactions are issued when this
register is read to or written from.
Figure 10.4.49 G2P Configuration Data Register
10-82
Chapter 10 PCI Controller
0xD1A4
Offset Address
Little Endian Mode Big Endian Mode
0xD1A4
0xD1A4
0xD1A6
0xD1A4
0xD1A5
0xD1A6
0xD1A7
Description
0xD1A4
0xD1A6
0xD1A4
0xD1A7
0xD1A6
0xD1A5
0xD1A4
16
: Type
: Initial value
0
: Type
: Initial value
Read/Write
R/W