Analog Devices ADSP-SC58 Series Hardware Reference Manual page 3586

2. Trigger
3. Interrupt request
4. Debug
SWU Interrupts
All interrupt requests and events from each match block are merged into common outputs.
SWU Status and Errors
SWU status and errors are reported in the
read attempt is made to the MMR address space of the SWU and the register does not exist. This error is the only
one the SWU records. The register contains bits that perform the following functions.
• Indicate whether a particular match group sampled a transaction that is below a minimum target or above a
maximum target in bandwidth mode.
• Indicate whether a watchpoint match occurred for each match group.
• Indicate whether an interrupt request was triggered due to a match event from one of the match groups.
Triggers
The SWU can be either a trigger master or a trigger slave depending on the trigger routing unit (TRU) configura-
tion. As a trigger master, programs must set the SWU_CTL[n].TRGEN bit so that when a match condition is met,
a trigger event is generated. Each SWU in the system can also be a trigger slave when mapped as one in the TRU.
When the SWU is a slave, a trigger event activates the SWU by automatically setting the SWU_GCTL.EN bit. Since
the SWU can be automatically enabled through a trigger event, programs must pre-configure the SWU before ena-
bling the TRU. Furthermore, although a trigger event can enable the SWU as a slave, to disable the SWU, programs
must manually clear the SWU_GCTL.EN bit.
SWU Programming Model
Program the appropriate registers to use the SWU. Each control register configures aspects such as:
• The direction of monitoring (reads or writes)
• Whether SWU uses bandwidth mode or watchpoint mode
• The setup of events that are triggered when a condition is met while monitoring using the SWU
Configure supplemental registers such as the lower (SWU_LA[n]) and upper (SWU_UA[n]) address boundaries
before enabling the SWU.
Once the SWU has been enabled and the monitoring conditions are met, events are generated when configured.
The global status register (SWU_GSTAT) can be read to observe the status of the units.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
SWU_GSTAT register. The SWU records an address error when a write or
SWU Event Control
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