Analog Devices ADSP-SC58 Series Hardware Reference Manual page 3607

56 System Debug and Trace Unit (DBG)
The system debug and trace unit is based on ARM Core Sight technology. CoreSight™ is a set of architecture speci-
fications defining debug and trace architecture. The processor uses CoreSight infrastructure to provide industry
standard debug and trace capabilities.
http://infocenter.arm.com/help/
The applicable documentation for more details about the ARM CoreSight feature includes:
• CoreSight PFT Architecture Specification , ARM IHI 0035B (PFT)
• System Trace Macrocell, Programmers' Model Architecture Specification, ARM IHI 0054A (STM)
• CoreSight Trace Memory Controller, ARM DDI0461B (TMC)
• CoreSight Components Technical Reference Manual, ARM DDI 0314H (TPIU)
• Embedded Cross Trigger Technical Reference Manual, ARM DDI 0291A
• ETM Architecture Specification, ARM IHI0014Q
• ETM for A5 Technical Reference Manual, DDI0435C
DBG Features
The system debug and trace unit contains the following features.
• System JTAG TAP controller for system debug features, boundary scan, and public JTAG features
• A debug interface to cores, and other system resources
• Direct and run-time access to the memory system and system MMRs
• Direct control over system reset
• Support for debug immediately after reset (boot debug)
• Group halt (debug event immediately halts all specified endpoints)
• Real-time on-chip visibility is made available to all developers, including software developers
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
System Debug and Trace Unit (DBG)
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