Analog Devices ADSP-SC58 Series Hardware Reference Manual page 3558

SCB Architectural Concepts
SCB Block Diagram
The following figures show the SCB block diagram. For DMA channel assignments for the peripherals shown in the
SCB Block Diagram figure, see the DMA Channel Peripherals Controlled by SCBs table following the figure.
Figure 54-3: SCB Block Diagram
There are two types of peripherals that use DMA. The first have dedicated DMA channels controlled by the Dedica-
ted DMA Engine (DDE) and have the same operating modes (see
gramming model (DMA Channel Programming
54–4
MASTER OUPUTS
SCLK0
SPORT0, HALF A
SPORT0, HALF B
SPORT1, HALF A
SCB1
SPORT1, HALF B
SPORT2, HALF A
SPORT2, HALF B
SPORT3, HALF A
SPORT3, HALF B
Standard BW MDMA0 (CRC)
SPORT4, HALF A
SPORT4, HALF B
SPORT5, HALF A
SPORT5, HALF B SCB2
SPORT6, HALF A
SPORT6, HALF B
SPORT7, HALF A
SPORT7, HALF B
Standard BW MDMA1 (CRC)
10/100/1000 EMAC
USB0
SCB3
SDIO
SINC
UART0, Tx
UART0, Rx
SCLK1
SPI0, Rx
SPI0, Tx
SPI1, Rx
SCB4
SPI1, Tx
SPI2, Rx
SPI2, Tx
EPPI, f0
EPPI, f1
SCLK0
FIR
HAE0 Tx
HAE, Rx0
SCB5
HAE, Rx1
UART1, Rx
UART1, Tx
10/100 EMAC
IIR
SCB6
UART2, Rx
UART2, Tx
Crypto
USB1
SCB7
EMDMA0 Channel 0/1
LPCLK
LP0
LPCLK-SYSCLK
CDC
LP1
SYSCLK
MLB
SCB8
DBG
ETR
PCIe
Medium BW MDMA2
High BW MDMA3
FFTA (High BW)
Model). The second type is not controlled by the DDE. These
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
SLAVE INPUTS
SCB1
SCB2
SCB3
SCB4
SCB5
SCB6
SCB7
SCB8
DMA Operating Modes) and use the same pro-