Renesas R-IN32M3 Series User Manual page 9

6.16 SII EEPROM Interface Registers ................................................................................................................... 100
6.16.1 EEPROM Configuration Register (EEP_CONF) .................................................................................. 100
6.16.2 EEPROM PDI Access State Register (EEP_STATE) ........................................................................... 101
6.16.3 EEPROM Control/Status Register (EEP_CONT_STAT)...................................................................... 102
6.16.4 EEPROM Address Register (EEP_ADR) .............................................................................................. 103
6.16.5 EEPROM Data Register (EEP_DATA) ................................................................................................. 104
6.17 MII Management Interface Registers ............................................................................................................. 105
6.17.1 MII Management Control/Status Register (MII_CONT_STAT) ........................................................... 105
6.17.2 PHY Address Register (PHY_ADR) ..................................................................................................... 106
6.17.3 PHY Register Address Register (PHY_REG_ADR) ............................................................................. 107
6.17.4 PHY Data Register (PHY_DATA) ........................................................................................................ 107
6.17.5 MII Management ECAT Access State Register (MII_ECAT_ACS_STAT) ......................................... 108
6.17.6 MII Management PDI Access State Register (MII_PDI_ACS_STAT) ................................................. 109
6.17.7 PHY Port Status n Register (PHY_STATUSn) ..................................................................................... 110
6.18 FMMU Registers ............................................................................................................................................ 111
6.18.1 FMMU Logical Start Address Register m (FMMUm.L_START_ADR) .............................................. 111
6.18.2 FMMU Length Register m (FMMUm.LEN) ......................................................................................... 111
6.18.3 FMMU Logical Start Bit Register m (FMMUm.L_START_BIT) ........................................................ 112
6.18.4 FMMU Logical Stop Bit Register m (FMMUm.L_STOP_BIT) ........................................................... 112
6.18.5 FMMU Physical Start Address Register m (FMMUm.P_START_ADR) ............................................. 113
6.18.6 FMMU Physical Start Bit Register m (FMMUm.P_START_BIT) ....................................................... 113
6.18.7 FMMU Type Register m (FMMUm.TYPE) .......................................................................................... 114
6.18.8 FMMU Activate Register m (FMMUm.ACT) ...................................................................................... 114
6.19 SyncManager Registers .................................................................................................................................. 115
6.19.1 SyncManager Physical Start Address Register m (SMm.P_START_ADR) ......................................... 115
6.19.2 SyncManager Length Register m (SMm.LEN) ..................................................................................... 115
6.19.3 SyncManager Control Register m (SMm.CONTROL).......................................................................... 116
6.19.4 SyncManager Status Register m (SMm.STATUS) ................................................................................ 117
6.19.5 SyncManager Activate Register m (SMm.ACT) ................................................................................... 118
6.19.6 SyncManager PDI Control Register m (SMm.PDI_CONT) .................................................................. 119
6.20 Distributed Clocks Registers........................................................................................................................... 120
6.20.1 DC Receive Time Registers ................................................................................................................... 120
6.20.2 DC Time Loop Control Unit Registers .................................................................................................. 121
6.20.3 Cyclic Unit Control Registers ................................................................................................................ 126
6.20.4 SYNC Output Unit Registers ................................................................................................................. 127
6.20.5 Latch Input Unit Registers ..................................................................................................................... 132
6.20.6 SyncManager Event Times Registers .................................................................................................... 139
6.21 ETC Registers ................................................................................................................................................. 141
6.21.1 Product ID Register (PRODUCT_ID) ................................................................................................... 141
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