Dc_Sync1_Cyc_Time; Dc_Latch0_Cont - Renesas R-IN32M3 Series User Manual

R-IN32M3-EC User's Manual
6.20.4.9 SYNC1 Cycle Time Register (DC_SYNC1_CYC_TIME)
DC_SYNC1_CYC_TIME is used to set the time between SYNC1 pulse and SYNC0 pulse.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
DC_SYNC1_
CYC_TIME
ECAT
R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W)
PDI
R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W)
Bit Position Bit Name
31 to 0 SYNC1CYC
Remark: Writing to this register depends on the setting of bit 0 in the cyclic unit control register
(DC_CYC_CONT: 0x0980).
6.20.5 Latch Input Unit Registers
6.20.5.1 Latch0 Control register (DC_LATCH0_CONT)
DC_LATCH0_CONT is used to control the edge function of Latch0 input signal.
7
DC_LATCH0_
0
CONT
0
ECAT
0
PDI
Bit Position Bit Name
1 NEGEDGE
0 POSEDGE
Remark: Writing to this register depends on the setting of bit 4 in the cyclic unit control register
(DC_CYC_CONT: 0x0980).
R18UZ0003EJ0501
Jan. 12, 2021
SYNC1CYC
These bits set the time between SYNC1 pulse and SYNC0 pulse in ns.
6 5 4
0 0 0
0 0 0
0 0 0
Indicates the function of Latch0 negative edge.
0: Continuous latch active
1: Single event (only first event is active)
Indicates the function of Latch0 positive edge.
0: Continuous latch active
1: Single event (only first event is active)
6. EtherCAT Slave Controller Function
8
Description
3 2 1
0 0
0 0 R/(W) R/(W)
0 0 R/(W) R/(W)
Description
7 6 5 4 3 2 1 0
400E 09A4H
Initial Value
0000 0000H
0 Address Initial Value
400E 09A8H
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Address
00H