Renesas R-IN32M3 Series User Manual page 150

R-IN32M3-EC User's Manual
6.20.5.7 Latch1 Time Positive Edge Register (DC_LATCH1_TIME_POS)
DC_LATCH1_TIME_POS indicates the system time at the positive edge of Latch1 input signal.
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
DC_
LATCH1_
TIME_POS
ECAT
R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack)
PDI
R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
ECAT
R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack)
PDI
R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack) R(ack)
Bit Position Bit Name
63 to 0 SYSTIME
Remarks 1. Bits 63to 8 are internally latched (ECAT/PDI independently) when bits 7 to 0 are read, which
guarantees reading a consistent value.
2. Clearing the Latch1 status flag function depends on the setting of bit 5 in the cyclic unit
control register (DC_CYC_CONT: 0x0980).
R18UZ0003EJ0501
Jan. 12, 2021
SYSTIME
SYSTIME
These bits indicate the system time captured at the positive edge of Latch1 input signal.
Reading this register clears bit 0 in the Latch1 status register (DC_LATCH1_STAT:
0x09AF).
6. EtherCAT Slave Controller Function
8 7 6 5 4 3
Description
Address
400E 09C0H
Initial Value
0000 0000
0000 0000H
2 1 0
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