Renesas R-IN32M3 Series User Manual page 25

R-IN32M3-EC User's Manual
Remark: Pins of the external memory interface pins other than BUSCLK are input pins while the
internal reset signal (HRESETZ) is at its active level.
Notes 1. While the synchronous burst access memory controller is in use, these signals are
multiplexed with the address signals if the ADMUXMODE pin is driven high.
ADMUXMODE = 0: MD0-MD31 (Separate address and data lines)
ADMUXMODE = 1: MD0-MD31/MA0-MA31 (Multiplexed address and data lines)
2. These pins are only available when the synchronous burst access memory controller is in use.
3. This pin functions as BCYSTZ when the asynchronous SRAM memory controller is in use and
as ADVZ when the synchronous burst access memory controller is in use.
4. This pin functions as A1-A27 and D0-D31 functions when the asynchronous SRAM memory
controller is in use and as MA0-MA26 and MD0-MD31 functions when the synchronous burst
access memory controller is in use.
R18UZ0003EJ0501
Jan. 12, 2021
2. Pin Functions
Page 12 of 224