Renesas R-IN32M3 Series User Manual page 118

R-IN32M3-EC User's Manual
6.17 MII Management Interface Registers
6.17.1 MII Management Control/Status Register (MII_CONT_STAT)
MII_CONT_STAT is used to control the MII management interface and to indicate the status.
15 14
MII_CONT_
STAT
R R
ECAT
R R
PDI
Bit Position Bit Name
15 BUSY
14 CMDERR
13 READERR
9, 8 COMMAND
7 to 3 PHYOFFSET
2 MILINK
1 PDICTRL
0 WREN
R18UZ0003EJ0501
Jan. 12, 2021
13 12 11 10 9
0 0 0
R/(W) R/(W) R/(W)
0 0 0
R/(W) R/(W) R/(W)
0 0 0
Indicates that the MII management interface is busy.
0: The MII management interface is idle
1: The MII management interface is busy
Indicates the generation of a command error.
0: The last command was successful
1: Invalid command or write command without write enable
This bit is cleared with a valid command or by writing "00" to command bits 9 and 8.
Indicates the generation of a read error.
0: No read error
1: Read error occurred (PHY or register not available)
This bit is cleared by writing to this register.
Command
Write: Initiates the command below
Read: Indicates the currently executed command
Commands:
00: No command/MI idle (clear error bits)
01: Read
10: Write
Others: Reserved/invalid commands (do not issue)
Indicates the PHY address offset.
Indicates whether the MI link detection can be used.
0: Not available
1: Available
Indicates that whether the MII management interface control is offered to PDI.
0: ECAT only has the control
1: PDI also has the control
This bit is controlled by the MII management ECAT access state register
(MII_ECAT_ACS_STAT: 0x0516) and the MII management PDI access state register
(MII_PDI_ACS_STAT: 0x0517).
Write Enable
0: Write disabled
1: Write enabled
This bit is always 1 if PDI has the MII management interface control.
6. EtherCAT Slave Controller Function
8 7 6 5 4 3
PHYOFFSET
R R R R R
R R R R R
Description
Address
2 1 0
400E 0510H
R/(W)
R R
R R R
Page 105 of 224
Initial
Value
0006H