Renesas R-IN32M3 Series User Manual page 183

R-IN32M3-EC User's Manual
7.4.17 Register 24 - FEQ Monitor Register
Register 24 sets the FEQ monitor function of Ethernet PHY and shows the FEQ results.
15 14 13
MR24
RW RW RW
Bit Position Bit Name
15 to 0 FEQ_DELTA
(Write)
FEQ_VAL
(Read)
R18UZ0003EJ0501
Jan. 12, 2021
12 11 10 9 8
FEQ_DELTA / FEQ_VAL
RW RW RW RW RW
These bits set the amount of change in FEQ2 factor allowed for the value of the
reference that has been latched. When the BER_CNT_LINK_EN bit in register 23
is 1, if the value of FEQ2 exceeds this value, FEQ interrupt is generated and the
link is down.
FFFF: Disable FEQ monitor function and continue to latch on the FEQ2 factor
ongoing.
FFFE: The current reference value can be read from this register. The value of
FEQ_DELTA does not change.
Others: Set the threshold of amount of change. FEQ monitor function starts to
work with setting this value.
These bits show bits 17 to 2 of FEQ2 coefficient latched as a reference when write
FFFE to FEQ_DELTA.
Others: Current FEQ2 coefficient.
7 6 5 4 3
RW RW RW RW RW
Description
7. Ethernet PHY Function
2 1 0
Register Address
18H
Initial Value
0000H
RW RW RW
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