Dc_Latch1_Time_Pos; Dc_Latch1_Time_Neg - Renesas R-IN32M3 Series User Manual

R-IN32M3-EC User's Manual
6.20.5.4 Latch1 Status Register (DC_LATCH1_STAT)
DC_LATCH1_STAT indicates the status of Latch1 input signal.
7
DC_LATCH1_
0
STAT
0
ECAT
0
PDI
Bit Position Bit Name
2 PINSTATE
1 EVENTNEG
0 EVENTPOS
R18UZ0003EJ0501
Jan. 12, 2021
6 5 4
0 0 0
0 0 0
0 0 0
Indicates the status of Latch1 input pin.
Indicates the event of Latch1 input negative edge.
0: Negative edge is not detected or in continuous mode
1: Negative edge is detected in single event mode only.
The flag is cleared by reading the Latch1 time negative edge register
(DC_LATCH1_TIME_NEG: 0x09C8).
Indicates the event of Latch1 input positive edge.
0: Positive edge is not detected or in continuous mode
1: Positive edge is detected in single event mode only.
The flag is cleared by reading the Latch1 time positive edge register
(DC_LATCH1_TIME_POS: 0x09C0).
6. EtherCAT Slave Controller Function
3 2 1
0
0 R R
0 R R
Description
0 Address Initial Value
400E 09AFH
R
R
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