Renesas R-IN32M3 Series User Manual page 119

R-IN32M3-EC User's Manual
Remark: Write access depends on the assignment of the management interface (ECAT/PDI). Write
access is generally blocked if the management interface is busy (bit 15 in this register is 1).
Note: The write enable bit 0 is self-cleared at the SOF of the next frame (or at the end of the PDI
access), and command bits 9 and 8 are also self-cleared after the command is executed (after
the busy ends).
Writing "00" to command bits will clear the error bits 14 and 13. The command bits are
cleared after the command is executed.
6.17.2 PHY Address Register (PHY_ADR)
PHY_ADR is used to set the PHY address.
7
0
PHY_ADR
0
ECAT
0
PDI
Bit Position Bit Name
4 to 0 PHYADDR
Remark: Write access depends on the assignment of the management interface (ECAT/PDI). Write
access is generally blocked if the management interface is busy (bit 15 in the MII management
control/status register (MII_CONT_STAT: 0x0510) is 1).
R18UZ0003EJ0501
Jan. 12, 2021
6 5 4
0 0
0 0 R/(W) R/(W)
0 0 R/(W) R/(W)
PHY Address
6. EtherCAT Slave Controller Function
3 2 1
PHYADDR
R/(W) R/(W) R/(W)
R/(W) R/(W) R/(W)
Description
0 Address Initial Value
400E 0512H
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