Renesas R-IN32M3 Series User Manual page 165

R-IN32M3-EC User's Manual
7.3 Power-Down Mode
The hardware power-down mode, software power-down mode, and energy detection power-mode are available, and each
of the power-down modes is described as follows.
7.3.1 Hardware Power-Down Mode
The operation is shifted to hardware power-down mode by setting 1 to bit 2 (P0PHYEN) or bit 5（P1PHYEN) in the
Ethernet PHY operation mode control register (PHYMD). The Ethernet PHY does not work at all in hardware
power-down mode and MII management registers cannot be accessed. The power consumption of the port will be almost
0. To wake up from the hardware power-down mode, set 0 to bit 2 (P0PHYEN) or bit 5 (P1PHYEN) in the Ethernet PHY
operation mode control register (PHYMD). When returning from the hardware power-down mode, both analog and
digital circuits are initialized by the Ethernet PHY and so are MII management registers. Hardware power-down mode
must be kept for more than 100us.
7.3.2 Software Power-Down Mode
The operation is shifted to software power-down mode by setting 1 to bit 11 (POWERDOWN) in MII management
register 0 with the Ethernet PHY. The IDLE signal is not output in the transition to software power-down mode and in
software power-down mode. However, MII management registers can be accessed and the Ethernet PHY can be
controlled in software power-down mode. To wake up from the software power-down mode, set 0 to bit 11
(POWERDOWN) in MII management register 0. The digital circuits are initialized automatically by the Ethernet PHY at
the end of software power-down mode. However, note that some bits in MII management registers are not initialized.
This applies to the bit described as "NASR" in Section 7.4, MII Management Registers in Ethernet PHY.
7.3.3 Energy Detection Power-Down Mode
The operation is shifted to energy detection power-down mode by setting 1 to bit 13 (EDPWRDOWN) in MII
management register 17 with the Ethernet PHY. Note that the operation does not shift to the energy detection
power-down mode when auto-negotiation is enabled. In this mode, the Ethernet PHY will not output anything except for
several modules such as the serial management interface when there is no input of link pulse or packet signal to the
Ethernet PHY. The Ethernet PHY will be reset automatically to the speed before becoming energy detection power-down
mode, when link pulse or packet signal is input to the Ethernet PHY in this state. At that time, receiving the first and the
next signals may be failed because of the detection of link pulse and packet signal.
Set 0 to bit 13 (EDPWRDOWN) in MII management register 17 to end the energy detection power-down mode and
return to the normal mode.
R18UZ0003EJ0501
Jan. 12, 2021
7. Ethernet PHY Function
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