Renesas R-IN32M3 Series User Manual page 179

R-IN32M3-EC User's Manual
7.4.11 Register 18 - Special Mode Register
Register 18 specifies the mode setting of Ethernet PHY.
15 14 13
(RESERVED)
MR18
RW R
Bit Position Bit Name
15to 11 (RESERVED)
10 FX_MODE
9 (RESERVED)
8 to 5 PHY_MODE[3:0]
4to 0 PHY_ADD[4:0]
R18UZ0003EJ0501
Jan. 12, 2021
12 11 10 9
R RW RW RW RW
NASR
Reserved (Write 0 and ignore reading)
Enables/Disables the 100BASE-FX mode. When enabling the 100BASE-FX
mode, PHY_MODE (bits 8 to 5 in register 18) must be 0011 or 0010.
0: Disabled (10BASE-T/100BASE-TX mode)
1: Enabled
Reserved (Write 0 and ignore reading)
These bits set the PHY operating mode.
PHY_MODE
[3:0]
0000 10BASE-T
0001 10BASE-T
0010 100BASE-TX/FX
0011 100BASE-TX/FX
0100 100BASE-T
0101 100BASE-T
repeater mode
0110 Power-down
mode
(For testing)
0111 All
1000 All
1001
1010
1011
1100
1101
1110
1111 Loopback/Isolate
These bits specify the PHY address. Setting of PHY_ADD[0] is ignored and 0 is
assigned to port 0 while 1 to port 1.
8 7 6 5
PHY_MODE[3:0]
RW RW RW RW
NASR NASR NASR NASR NASR
Description
Speed Duplex
Half-duplex
Full-duplex
Half-duplex
Full-duplex
Half-duplex
Half-duplex
-
Both sides
Full-duplex force by
parallel detection
Half-duplex by
parallel
detection(standard)
-
7. Ethernet PHY Function
4 3 2 1 0
PHY_ADD[4:0]
RW RW RW RW RW
NASR NASR NASR NASR
Auto negotiation
Invalid
Invalid
Invalid. Enable CRS of sending
and receiving.
Invalid. Enable CRS of sending.
Valid. Enable CRS of sending
and receiving.
Valid. Enable CRS of receiving.
-
Valid
Enable quick auto negotiation.
Select timing by bit 1 and bit
Note 1
0 .
- (Internal loop-back mode)
Register Address
12H
Initial Value
00E0H
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