Renesas R-IN32M3 Series User Manual page 189

R-IN32M3-EC User's Manual
7.4.23 Register 30 - Interrupt Factor Mask Register
Register 30 enables/disables interrupt factors of Ethernet PHY. "0" is invalid (mask), while "1" is valid.
15 14 13
MR30
(RESERVED)
R R R
Bit Position Bit Name
15 to 13 (RESERVED)
12 INT12_MASK
11 INT11_MASK
10 INT10_MASK
9 INT9_MASK
8 (RESERVED)
7 INT7_MASK
6 INT6_MASK
5 INT5_MASK
4 INT4_MASK
3 INT3_MASK
2 INT2_MASK
1 INT1_MASK
0 (RESERVED)
R18UZ0003EJ0501
Jan. 12, 2021
12 11 10 9 8
RW RW RW RW R
Reserved (Write 0 and ignore reading)
Clipping
Maxlvl
BER counter trigger
FEQ trigger
Reserved (Write 0 and ignore reading)
Energy detection of the line
Auto-negotiation is complete
Remote fault detection
Link down
Auto-negotiation is complete and receive the last FLP
Parallel detection failure
Auto-negotiation shifts to the complete acknowledge state.
Reserved (Write 0 and ignore reading)
7 6 5 4 3
RW RW RW RW RW
Description
7. Ethernet PHY Function
2 1 0
Register Address
1EH
Initial Value
0000H
RW RW R
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