Renesas R-IN32M3 Series User Manual page 90

R-IN32M3-EC User's Manual
Bit Position Bit Name
0 FWDRULE
Notes 1. Loop configuration changes are delayed until the end of a currently received or
transmitted frame at the port.
2. The possibility of RX FIFO size reduction depends on the clock source accuracy of every
connected EtherCAT devices (master, slave, etc.). The RX FIFO size as default is sufficient
for 100 ppm accuracy, but the FIFO size of 0 to 3 is possible with 25 ppm accuracy.
6.10.4 Physical Read/Write Offset Register (PHYSICAL_RW_OFFSET)
PHYSICAL_RW_OFFSET is used to set offset size between the read address and the write address in the R/W
command.
15 14
PHYSICAL_
RW_OFFSET
ECAT
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
PDI
R R
Bit Position Bit Name
15 to 0 RWOFFSET
R18UZ0003EJ0501
Jan. 12, 2021
Forwarding Rule
0: EtherCAT frames are processed. Non-EtherCAT frames are forwarded without
processing.
1: EtherCAT frames are processed. Non-EtherCAT frames are destroyed.
The source MAC address is changed for every frame (SOURCE_MAC[1] is set to 1
(locally administered address)) regardless of the forwarding rule.
13 12 11 10 9
RWOFFSET
R R R R R
Offset of R/W Commands (FPRW, APRW) between Read address and Write address
RD_ADR = ADR
WR_ADR = ADR + R/W-offset
6. EtherCAT Slave Controller Function
Description
8 7 6 5 4 3
R R R R R R
Description
Address
2 1 0
400E 0108H
R R R
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Initial
Value
0000H