Renesas R-IN32M3 Series User Manual page 116

R-IN32M3-EC User's Manual
Remark: Write access depends on the assignment of the EEPROM interface (ECAT/PDI). Write access is
generally blocked if the EEPROM interface is busy (bit 15 = 1).
Notes 1. The error bits are cleared by writing "000" (or any valid command) to command bits 10 to 8.
. The ECAT write enable bit 0 is self-cleared at the SOF of the next frame, and command bits
2
10 to 8 are also self-cleared after the command is executed (after the EEPROM busy ends).
Writing "000" to command bits 10 to 8 will clear the error bits 14 and 13. Command bits 10 to
8 are ignored, if the acknowledge/command error bit 13 is 1.
6.16.4 EEPROM Address Register (EEP_ADR)
EEP_ADR is used to set the EEPROM address to be accessed.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
EEP_ADR
ECAT R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W)
PDI R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W)
Bit Position Bit Name
31 to 0 ADDRESS
Remark: Write access depends on the assignment of the EEPROM interface (ECAT/PDI). Write access is
generally blocked if the EEPROM interface is busy (bit 15 in the EEPROM control/status
register (EEP_CONT_STAT: 0x0502) is 1).
R18UZ0003EJ0501
Jan. 12, 2021
ADDRESS
EEPROM Address
0: First word (= 16 bits)
1: Second word
...
Actually used EEPROM address bits:
[9:0]: EEPROM size up to 16 Kbits
[17:0]: 32 Kbit – 4 Mbit EEPROM size
6. EtherCAT Slave Controller Function
8 7 6 5 4 3
Description
Address
2 1 0
400E 0504H
Initial Value
0000 0000H
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