Dc_Latch1_Cont; Dc_Latch0_Stat; Dc_Latch0_Time_Pos; Dc_Latch0_Time_Neg - Renesas R-IN32M3 Series User Manual

R-IN32M3-EC User's Manual
6.20.5.2 Latch1 Control Register (DC_LATCH1_CONT)
DC_LATCH1_CONT is used to control the edge function of Latch1 input signal.
7
DC_LATCH1_
0
CONT
0
ECAT
0
PDI
Bit Position Bit Name
1 NEGEDGE
0 POSEDGE
Remark: Writing to this register depends on the setting of bit 5 in the cyclic unit control register
(DC_CYC_CONT: 0x0980).
6.20.5.3 Latch0 Status Register (DC_LATCH0_STAT)
DC_LATCH0_STAT indicates the status of Latch0 input signal.
7
DC_LATCH0_
0
STAT
0
ECAT
0
PDI
Bit Position Bit Name
2 PINSTATE
1 EVENTNEG
0 EVENTPOS
R18UZ0003EJ0501
Jan. 12, 2021
6 5 4
0 0 0
0 0 0
0 0 0
Indicates the function of Latch1 negative edge.
0: Continuous latch active
1: Single event (only first event is active)
Indicates the function of Latch1 positive edge.
0: Continuous latch active
1: Single event (only first event is active)
6 5 4
0 0 0
0 0 0
0 0 0
Indicates the status of Latch0 input pin.
Indicates the event of Latch0 input negative edge.
0: Negative edge is not detected or in continuous mode
1: Negative edge is detected in single event mode only.
The flag is cleared by reading the Latch0 time negative edge register
(DC_LATCH0_TIME_NEG: 0x09B8).
Indicates the event of Latch0 input positive edge.
0: Positive edge is not detected or in continuous mode
1: Positive edge is detected in single event mode only.
The flag is cleared by reading the Latch0 time positive edge register
(DC_LATCH0_TIME_POS: 0x09B0).
6. EtherCAT Slave Controller Function
3 2 1
0 0
0 0 R/(W) R/(W)
0 0 R/(W) R/(W)
Description
3 2 1
0
0 R R
0 R R
Description
0 Address Initial Value
400E 09A9H
0 Address Initial Value
400E 09AEH
R
R
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