Renesas R-IN32M3 Series User Manual page 12

Figure 3.1 Memory Map (All) .............................................................................................................................. 41
Figure 3.2 Memory Map (APB Peripheral Registers Area) ................................................................................. 42
Figure 3.3 Memory Map (External Memory Area) .............................................................................................. 43
Figure 3.4 Memory Map (CC-Link Master Area) ................................................................................................ 43
Figure 3.5 External MCU Interface Area ............................................................................................................. 44
Figure 6.1 Peripheral Circuit of EtherCAT Slave Controller ............................................................................... 53
Figure 6.2 Reset Circuit of EtherCAT Slave Controller ..................................................................................... 143
Figure 6.3 Reset Timing of EtherCAT Slave Controller (In case of reset request by ECAT/PDI) .................... 144
Figure 6.4 Reset Timing of EtherCAT Slave Controller (In case of reset by CATRESET register) ................. 144
Figure 7.1 Preamble of Ethernet Frames ............................................................................................................ 145
Figure 7.2 Operation when Cable is Disconnected ............................................................................................ 148
Figure 7.3 Operation when Cable is Short-Circuited ......................................................................................... 148
Figure 7.4 Cable Diagnostic Process Flow ......................................................................................................... 150
Figure 8.1 Basic Circuit Configuration of Ports ................................................................................................. 184
Figure 8.2 Port Registers (in 8-Bit Notation) ..................................................................................................... 191
Figure 8.3 Port Registers (in 16-Bit Notation) ................................................................................................... 192
Figure 8.4 Port Registers (in 32-Bit Notation) ................................................................................................... 193
Figure 8.5 Port Mode Registers (in 8-Bit Notation): .......................................................................................... 194
Figure 8.6 Port Mode Registers (in 16-Bit Notation) ......................................................................................... 195
Figure 8.7 Port Mode Registers (in 32-Bit Notation) ......................................................................................... 196
Figure 8.8 Port Mode Control Registers (in 8-Bit Notation) .............................................................................. 197
Figure 8.9 Port Mode Control Registers (in 16-Bit Notation) ............................................................................ 198
Figure 8.10 Port Mode Control Registers (in 32-Bit Notation) ............................................................................ 199
Figure 8.11 Port Function Control Registers (in 8-Bit Notation) ......................................................................... 200
Figure 8.12 Port Function Control Registers (in 16-Bit Notation) ....................................................................... 201
Figure 8.13 Port Function Control Registers (in 32-Bit Notation) ....................................................................... 202
Figure 8.14 Port Function Control Expansion Registers (in 8-Bit Notation) ....................................................... 203
Figure 8.15 Port Function Control Expansion Registers (in 16-Bit Notation) ..................................................... 204
Figure 8.16 Port Function Control Expansion Registers (in 32-Bit Notation) ..................................................... 205
Figure 8.17 Port Pin Input Registers (in 8-Bit Notation) ..................................................................................... 206
Figure 8.18 Port Pin Input Registers (in 16-Bit Notation) ................................................................................... 207
Figure 8.19 Configuration of Trigger-Synchronous Ports .................................................................................... 223
Contents of Figures
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