Renesas R-IN32M3 Series User Manual page 241

R-IN32M3-EC User's Manual
Rev. Date
4.01 Feb. 28, 2017
5.00 Dec. 28, 2018
5.01 Jan. 12, 2021
Page
150 7.2.4 Fast Link-Loss Detection Function
Explanation of error count method modified
151 7.3.1 Hardware Power-Down mode
Minimum reset time added
153 7.4 MII Management Registers in Ethernet PHY
Explanation about the symbols below bit name of registers added
154-176 7.4.1 Register 0 – Control Register to 7.4.24 Register 31 – PHY Special
Control/Status Register
Description changed PHY Address to Register Address
179 7.5.3 Ethernet PHY Power-Up Status Register (PHYPUS)
Time for bits to be cleared added
180 7.6 LED signal added
6 1.5 Base Addresses of the System Registers Area
The description on the base addresses of the system registers area was
added.
18 2.1.7 DMA Interface Pins
The description on the section and caution was modified.
21 2.1.14 CC-Link Pins (Intelligent Device Station)
Functional descriptions of the CC-Link (intelligent device station) pins were
modified.
41, 44 3. Memory Maps
Note describing that the addresses the instruction RAM mirror area (768
Kbytes) where access actually occurs will change according to the select boot
mode, was added.
Figure 3.1 Memory Map (All)
Figure 3.5 External MCU Interface Space
183 8.2 Port Configuration
"Application and Operation" for the port function control registers and the port
function control expansion registers was modified.
183 8.2 Port Configuration
Caution on the port configuration was modified.
197 to 8.3.3 Port Mode Control Register (PMC, RPMC)
205 8.3.4 Port Function Control Registers (PFC, RPFC)
8.3.5 Port Function Control Expansion Registers (PFCE, RPFCE)
Notes on the multiplexed functions were modified.
—
Error corrected, description modified, and contents and expressions adjusted
3 1.2 Overview
55, 57 6.4 Functional Overview
145 7.1 Features
Description on no support of EtherCAT P was added.
Description
Summary
REVISION HISTORY
REVISION-4