Renesas R-IN32M3 Series User Manual page 100

R-IN32M3-EC User's Manual
6.12.4 SYNC/LATCH PDI Configuration Register (SYNC_LATCH_CONFIG)
SYNC_LATCH_CONFIG indicates the settings of SYNC output and LATCH input.
7
SYNC_LATCH_
CONFIG
R
ECAT
R
PDI
Bit Position Bit Name
7 SYNC1MAP
6 SYNCLAT1
5, 4 SYNC1OUT
3 SYNC0MAP
2 SYNCLAT0
1, 0 SYNC0OUT
Notes 1. This indicates the initial value until the EEPROM is loaded. After that, bits 7 and 3 change
depending on the value stored at address 0x0003 in the EEPROM.
The EEPROM value is only taken over at first EEPROM load after power-on or reset.
2. Though the bit always indicates SYNC output, Latch input is available. Use the chip level pin
multiplex function in order to switch SYNC output to LATCH input, and vice versa.
R18UZ0003EJ0501
Jan. 12, 2021
6 5 4
R R R
R R R
SYNC1 Mapped to Bit 3 in AL Event Request Register (AL_EVENT_REQ: 0x0220)
This bit always indicates 1 (enabled) in this LSI.
0: Disabled
1: Enabled
SYNC1/LATCH1 Configuration
This bit always indicates 1 in this LSI.
0: LATCH1 input
1: SYNC1 output
SYNC1 Output Driver/Polarity
These bits always indicate 10 (push-pull active high) in this LSI.
SYNC0 Mapped to Bit 2 in AL Event Request Register (AL_EVENT_REQ: 0x0220)
This bit always indicates 1 (enabled) in this LSI.
0: Disabled
1: Enabled
SYNC0/LATCH0 Configuration
This bit always indicates 1 in this LSI.
0: LATCH0 input
1: SYNC0 output
SYNC0 Output Driver/Polarity
These bits always indicate 10 (push-pull active high) in this LSI.
6. EtherCAT Slave Controller Function
3 2 1
R R R
R R R
Description
Note 2
Note 2
0 Address Initial Value
400E 0151H
R
R
Page 87 of 224
Note 1
EEH