User Manual
10/21/02
errors do not raise exceptions or cause the DMA engines to stop, so the Bus Watcher interrupt is likely to be
the only way they are reported.
READ ONLY, Read will clear all fields and the cor_ecc_int and bad_ecc_int interrupts
Bits
Name
7:0
reserved
17:8
tid
21:18
rid
24:22
dcode
29:25
reserved
30
mult_errors
31
reserved
63:32
notimp
Bits
Name
63:0
value
Bits
Name
63:0
data
Document
1250_1125-UM100CB-R
Table 35: Bus Watcher Error Status Register
bus_err_status - 00_1002_0880
Default
8'b0
Reserved
10'b0
Transfer ID that had error code. Top 4 bits indicate the initiator of the
transfer, see
more details on the what within the agent caused the transaction, see
Table 51 on page
4'b0
Responder ID identifies the agent that reported the error. See
Table 1 on page
3'b0
Data transfer error code. See
5'b0
Reserved
1'b0
Set to indicate multiple errors. The first fatal one, or the most recent non-
fatal one is logged (all were counted).
1'b1
Reserved. Reads as 1.
32'bx
Not Implemented.
Table 36: Bus Watcher Error Status Debug Register
bus_err_status_debug - 00_1002_08D0 READ ONLY
Default
64'hx
This register contains the same information as the bus_err_status
register, but reads do not have any side effects.
Table 37: Bus Watcher Error Data Registers
bus_err_data_0 - 00_1002_08A0
bus_err_data_1 - 00_1002_08A8
bus_err_data_2 - 00_1002_08B0
bus_err_data_3 - 00_1002_08B8
READ ONLY
Default
64'hx
Data from error transaction. The register number is address bits [4:3].
Register _0 contains ZBbus bits 255:192
Register _1 contains ZBbus bits 191:128
Register _2 contains ZBbus bits 127:64
Register _3 contains ZBbus bits 63:0
B r oadco m C orp or ati on
BCM1250/BCM1125/BCM1125H
Description
Table 1 on page 20
for the mapping. Low 6 bits may give
81.
20.
Table 6 on page
Description
Description
Section 4: System Control and Debug Unit
24.
Page
65
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