Broadcom BCM1250 User Manual page 255

User Manual
10/21/02
7.5.3.3 Host Interface Command Bits
7.5.4 Link Control Register
7.5.5 Link Configuration Register
7.5.8 Link Error Register
7.5.9 Link Frequency Capability
7.5.10 Feature Capability Register
7.5.11 Enumeration Scratchpad
7.5.12 Error Handling Register
7.5.13, 7.5.14 Memory Base/Limit Upper Bits
7.6 Interrupt Discovery and Configuration Capability Block
Document 1250_1125-UM100CB-R
The pass 2 BCM1250 does not implement the fields that are new in the revision 1.02
specification: Device Number, Chain Side, Host Hide, Act as Slave, Drop on Uninit. Interface
revision 3 and greater, used for the BCM1125H and later versions of the BCM1250, includes
these. The new Host Inbound End of Chain error (Bit 11) functionality is incorporated in the
MapNxaError bit in the HyperTransport Error Status Register
The interface does not implement the fields that are new in the revision 1.02 specification:
Isocronous Enable, LDTSTOP# Tristate Enable, Extended CTL time. None of the functionality
that these control is supported.
This register reflects the fact that the interface only supports 8 bit links and does not support
doubleword flow control.
The error conditions reported in this new register are reported in the HyperTransport Error
Status register (Table 153 on page
selection mode (allowing link frequencies outside the standard) then bit 4 is used for frequency
selection.
The link frequency capability register is only supported on revision 3 and greater of the
interface. On revision 2 (BCM1250 pass 2) it would have the value 16'h801F, indicating that
frequencies up to 600MHz are supported and there are vendor specific frequencies. On
revision 1 (BCM1250 pass 1) it would have the value 16'h800F, indicating that frequencies up
to 500MHz are supported and there are vendor specific frequencies.
The link feature capability register is only supported on revision 3 and greater of the interface.
On older revisions it would have the value 16'h0004.
This register is not implemented (its address collides with the SRI registers).
The functions in this new register are available in the HyperTransport Error Control register
(Table 152 on page 253).
These are not implemented since the interface constrains PCI style memory operations to the
low section of the address map, and has special rules for addresses above the 32-bit region.
This new capability block is not implemented. Generation of interrupt messages is done by
software, and is restricted to IntrInfo[55:32]=0 and IntrInfo[31:24]=F8 (i.e. compatibility with
revision 1.01 and earlier and the x86 specific interrupt restrictions).
B r oadco m C orp or ati on
BCM1250/BCM1125/BCM1125H
(Table 153 on page
254). Note that if the bridge is put into the direct frequency
Section 8: PCI Bus and HyperTransport Fabric Page
254).
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