Performance Monitoring Features; Zbbus Monitoring - Broadcom BCM1250 User Manual

BCM1250/BCM1125/BCM1125H
A value of 0 for the r2rIdle parameter nominally provides 1 cycle of non-overlap for the DQ lines at the physical
bank of SDRAMs being read first. At the physical bank that is the target of the second read, this nominal value
is reduced by the DQ delay between the two physical banks. The DQS non-overlap time is nominally 0, but
since both physical banks are driving the DQS lines low during the turnaround, there is nominally 0.5 cycle of
margin before a conflict occurs on the DQS lines at the first physical bank. Once again, at the second physical
bank of SDRAMs, this 0.5 cycle of nominal no conflict time is reduced by the DQS delay between the two
physical banks. Therefore it is unlikely that a system will require a non-zero value of the r2rIdle parameter.
To summarize, most systems using half-cycle CAS latency will set r2wIdle to a 1, w2rIdle to a 1, and r2rIdle to
a 0. Systems using SDRAMs with a whole-cycle CAS latency will set r2rIdle to 1 and the other parameters to
0. Systems configuring an n-1 value for tCrD will need to set r2wIdle to 1.
P
ERFORMANCE
The memory controller provides signals to the performance counters in the SCD (see
Performance Counters" on page
Add discussion.
ZB M
BUS ONITORING
The functionality described in this section in previous releases of the BCM1250 manual was for the
prototype chips only and is no longer available. The trace buffer in the SCD (See
Unit" on page
Page 134 Section 6: DRAM
M F
ONITORING EATURES
61).
70) should be used to monitor the ZBbus.
B r oadco m C orp or ati on
User Manual
10/21/02
Section: "System
"Trace
Document 1250_1125-UM100CB-R