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1
Broadcom BCM1250 manual available for free PDF download: User Manual
Broadcom BCM1250 User Manual (516 pages)
Brand:
Broadcom
| Category:
Computer Hardware
| Size: 7 MB
Table of Contents
Table of Contents
5
Section 1: Introduction
29
The Sibyte Broadband Processor Family
29
The BCM1250
30
Figure 1: BCM1250 Block Diagram
30
The BCM1125 and BCM1125H
31
Audience
31
Figure 2: BCM1125/H Block Diagram
31
Other Documentation
32
Terminology
33
Section 2: Signal Overview
35
BCM1250 Signal Groups
35
Figure 3: BCM1250 Signals
35
BCM1125/H Signal Groups
36
Figure 4: BCM1125/H Signals
36
Section 3: System Overview
37
Introduction
37
Figure 5: Logical Block Diagram of BCM1250 and BCM1125/H
37
Internal Registers
39
Figure 6: Internal Control and Status Register Alignment
39
Coherence
40
Ordering Rules and Device Drivers
42
CPU Speculative Execution
44
Error Conditions
45
Cache Error Exceptions
45
Bus Error Exceptions
46
CPU to CPU Communication (BCM1250 Only)
47
External Interrupts
47
Overview of the Zbbus Protocol
48
Table 1: Zbbus Agent Ids
48
Table 2: Zbbus Signals
48
Arbitration
49
Address Phase
50
Table 3: Zbbus Commands
50
Response Phase
51
Table 4: Zbbus Level 1 Cache Attributes
51
Data Phase
52
Table 5: Zbbus Byte Lane Assignments
52
Table 6: Zbbus Data Status Codes
52
Reset
54
Figure 7: Decision Tree for Memory Space Address Accesses
54
Table 7: Operation of Different Reset Sources
55
Table 8: Static Configuration Options
55
Clocks
59
Table 9: Core and Hypertransport Clock Settings
59
Figure 8: Clock Distribution Overview
61
Memory Map
62
Table 10: Overview of BCM1250 Physical Address Map
62
Figure 9: Memory Map
63
Table 11: Address Map Details
64
Section 4: System Control and Debug Unit
69
Introduction
69
System Control
69
Table 12: System Identification and Revision Register
70
Table 13: Part Revisions
70
Table 14: Manufacturing Information Register
71
Table 15: System Configuration Register
71
Table 16: Scratch Register
73
Mailbox Registers
74
Table 17: Mailbox Registers
74
Interrupts
75
Table 18: Interrupt Mappings
75
Hypertransport Interrupts
76
Table 20: Delivery of Hypertransport Interrupts
77
The Full Interrupt Mapper
78
Figure 10: Per-CPU Interrupt Mapper (Replicated for each CPU; X = 0 or 1)
79
Table 21: Interrupt Registers
80
Table 22: Interrupt Sources
80
Timers
85
Watchdog Timers
85
General Timers
86
Timer Special Cases
86
Zbbus Cycle Count and Compare
86
Timer Registers
87
Table 23: Watchdog Timer Initial Count Registers
87
Table 24: Watchdog Timer Current Count Registers
87
Table 25: Watchdog Timer Configuration Registers
87
Table 26: General Timer Initial Count Registers
88
Table 27: General Timer Current Count Registers
88
Table 28: General Timer Configuration Registers
88
System Performance Counters
89
Table 29: Zbbus Count Register
89
Table 30: Zbbus Count Compare Registers
89
Table 31: System Performance Counter Configuration Registers
89
Table 32: System Performance Counters
90
Table 33: System Performance Counter Sources
90
Bus Watcher
92
Table 34: Bus Watcher Counters
92
Table 35: Bus Watcher Error Status Register
93
Table 36: Bus Watcher Error Status Debug Register
93
Table 37: Bus Watcher Error Data Registers
93
Table 38: Bus Watcher L2 ECC Counter Register
94
Table 39: Bus Watcher Memory and I/O Error Counter Register
94
Address Trapping
95
Table 40: Address Trap Trigger Index Register
96
Table 41: Address Trap Trigger Debug Register
96
Table 42: Address Trap Trigger Address Register
96
Table 43: Address Trap Range Top Address Registers
96
Table 44: Address Trap Range Base Address Registers
97
Table 45: Address Trap Configuration Registers
97
Trace Unit
98
Trigger Events
98
Table 46: Trace Event Register
100
Trigger Sequences
101
Table 47: Trace Sequence Control Registers
102
Using the Trace Buffer
104
Table 48: Trace Control Register
104
Table 49: Trace Buffer Address/Control Bundle
105
Reading the Trace Buffer
107
Table 50: Trace Entry Format and Read Order
107
Magic Decoder Ring for Using the Trace Buffer
109
Table 52: Encoded Byte Enables for CPU Transactions
110
Figure 11: Connections to Trace Logic
111
Trace Example 1: All CPU0 Activity
112
Section 5: L2 Cache
117
Introduction
117
Normal Operation
117
Using the L2 Cache as Memory
119
Figure 12: Level 2 Cache Way Disable Access Address
119
Standard RAM
120
Memory Locked in the L2 Cache
120
Table 53: Addresses for Memory Banks
120
Comments on Using the L2 as Memory
121
Reduced Cache Size
122
Cache Management Access
122
Figure 13: Cache Management Address
123
Table 54: Management Address
123
Standard Management Mode Accesses (both Ecc_Diag Address Bits Zero)
125
ECC Diagnostic Management Accesses (Ecc_Diag Bits Nonzero)
126
Table 55: ECC Diagnostic Operations
126
Cache Configuration Register
127
Example Startup Code to Clear the L2 Cache
127
Registers
128
Table 56: Level 2 Cache Tag Register
128
Table 57: Level 2 Cache Settings Register
128
Section 6: DRAM
131
Introduction
131
A Comment on the Term Bank
131
Memory Controller Architecture
132
Figure 14: Memory Controller Block Diagram
133
Memory Access Sequencing
135
Clock Ratios and Clocking Scheme
135
Table 58: Clock Speed
135
Table 59: Percent Deltas from Popular DIMM Frequencies
136
Memory Configurations
137
Mapping
137
Channel Select
137
Table 60: Mapping Physical Address to Memory Controller Address
137
Chip Select
138
Figure 15: Chip Select Options
138
Example Channel and Chip Select Configurations
140
Figure 16: Example Single Channel 128MB
140
Figure 17: Example 1GB with Two Chip Selects on One Channel
141
Figure 18: Example 1GB with Two Chip Selects Interleaved on One Channel
142
Figure 19: Example 1GB with Two Chip Selects Interleaved Across both Channels
143
Figure 20: Example 2GB with Two Chip Selects Interleaved on One Channel
144
Table 61: Address Bits Used by a Memory Channel
145
Table 62: Example for 128 Mbyte CS Region with 4K Rows, 1K Columns
146
Table 63: Example for 128 Mbyte CS Region with 4K Rows, 1K Columns, 64 Byte Interleave
146
Table 64: Example for 128 Mbyte CS Region with 4K Rows, 1K Columns, 128 Byte Interleave
147
Table 65: Example for 256 Mbyte Region with 4K Rows, 1K Columns, Two CS, and 128 Byte Interleave
147
Table 66: Example for 512 Mbyte Region with 4K Rows, 1K Columns, Four CS, and 128 Byte Interleave
147
Choosing Interleave Parameters
148
Page Policy
150
Supported Drams and Dimms
151
Ddr Sdrams
151
DDR Fcrams
151
Table 68: Supported Sdrams
151
Dimms
152
Larger Memory Systems
152
Ecc
153
SDRAM Timing
153
SDRAM Refresh
154
SDRAM Initialization and Commands
154
Table 69: Commands that Can be Issued through Mc_Dramcmd Register
154
I/O Control
156
Table 70: Adjustment Percentages and Multiplier for Values of DLL M
156
Figure 21: Timing Relationships Set by Dlls
158
Timing Parameter Guidelines
159
Figure 22: Nominal Windows at 133Mhz for First Edge of DQS for Various Settings of [Tcrd, Tcrdh, Tfifo]
159
Table 71: First DQS Window Opening and Closing (Typical)
160
Performance Monitoring Features
162
Zbbus Monitoring
162
Configuration Registers
163
Table 72: Memory Channel Configuration Register on BCM1250
163
Table 73: Memory Channel Configuration Register on BCM1125/H
164
Table 74: Memory Clock Configuration Register
166
Table 75: DRAM Command Register
167
Table 76: DRAM Mode Register
167
Table 77: SDRAM Timing Register
168
Table 79: Chip Select Start Address Register
169
Table 80: Chip Select End Address Register
169
Table 81: Chip Select Interleave Register
170
Table 82: Row Address Bits Select Register
170
Table 83: Column Address Bits Select Register
170
Table 84: Bank Address Bits Select Register
171
Table 85: Chip Select Attribute Register
171
Table 86: ECC Test Data Register
172
Table 87: ECC Test ECC Register
172
Section 7: DMA
175
DMA Controllers
175
Data Buffers and Descriptors
175
Figure 23: DMA Buffer
176
Table 88: Data Buffer Parameters
176
Table 89: Data Parameters
176
Figure 24: DMA Descriptor
177
Figure 25: Packet Spanning Three Buffers
178
Figure 26: DMA Descriptor Ring
179
Figure 27: DMA Descriptor Chain
181
Unaligned Buffer Descriptor Format for Ethernet DMA
182
Figure 28: Standard and Unaligned Buffer DMA Descriptors
182
DMA Coherence and Cache Options
183
DMA Configurations
184
Ethernet and Serial DMA Engines
185
Descriptor Count Watermarks
185
Completion Interrupts
186
Explicit Descriptor Interrupts
186
ASIC Mode Transfers
187
Figure 29: Packet Reception Flow Using DMA ASIC Mode
187
Figure 30: ASIC Mode Address Generation
188
Table 90: Address Used for ASIC Mode Transfers
188
Figure 31: Sending the Whole Packet in ASIC Mode
189
Figure 32: Sending a Packet Header in ASIC Mode
190
Table 93: Ethernet and Serial DMA Descriptor Base Address Register
194
Table 94: ASIC Mode Base Address
194
Table 95: Descriptor Count Register
194
Table 96: Current Descriptor a Debug Register
195
Table 97: Current Descriptor B Debug Register
195
Table 98: Current Descriptor Address Register
195
Table 100: DMA Descriptor First Doubleword
197
Table 101: DMA Descriptor Second Doubleword
197
Table 102: Unaligned Buffer Format DMA Descriptor First Doubleword
198
Table 103: Unaligned Buffer Format DMA Descriptor Second Doubleword
198
Table 104: Status Flags for Ethernet Receive Channel
199
Table 105: Option Flags for Ethernet Receive Channel
200
Table 106: Status Flags for Ethernet Transmit Channel
200
Table 107: Option Flags for Ethernet Transmit Channel
201
Table 108: Status Flags for Synchronous Serial Receive Channel
202
Table 109: Option Flags for Synchronous Serial Receive Channel
202
Table 110: Status Flags for Synchronous Serial Transmit Channel
202
Table 111: Option Flags for Synchronous Serial Transmit Channel
202
Data Mover
204
Data Mover Operation
204
CRC and Checksum Generators
206
Checksum Generation
206
CRC Generation
207
Table 112: Result in Memory of Appending the Result CRC[31:0]
207
Computation Sizes and Bandwidth
208
Table 113: Example CRC Configurations
208
Examples
209
Figure 33: Example 1 - TCP Checksum a Packet
209
Figure 34: Example 2 - Preparing an Iscsi Packet
210
Figure 35: Example 3 - Fragmenting an Iscsi Packet
211
Data Mover Control Registers
212
Table 114: Data Mover Descriptor Base Address Register
212
Table 115: Debug Data Mover Descriptor Base Address Register
212
Table 116: Data Mover Descriptor Count Register
213
Table 117: Data Mover Current Descriptor Address
213
Table 121: Data Mover Descriptor First Doubleword
215
Table 122: Data Mover Descriptor Second Doubleword
216
Section 8: PCI Bus and Hypertransport Fabric
218
Introduction
218
Figure 36: PCI and Hypertransport Organization
219
PCI and Hypertransport Address Range
220
Figure 37: Address Ranges for CPU Access to PCI and Hypertransport
221
Memory Mapped Devices
222
Hypertransport Expansion Space
222
Configuration Space
222
PCI I/O Space
223
The Southbridge, VGA and Subtractive Decode
223
Hypertransport End of Interrupt (EOI) Signaling Space
226
PCI Full Access Space
227
Special Hypertransport Space
227
Hypertransport Read Restrictions
228
Endian Policies
229
Figure 38: Little Endian System
229
Big Endian System: Match Byte Lanes
230
Figure 39: Match Byte Lane Endian Policy
230
Big Endian System: Match Bit Lanes
231
Figure 40: Match Bit Lane Endian Policy
231
Viewing Endian Policy as an Optimization
232
Table 123: PCI Base Address Register Use
233
Figure 41: PCI BAR0 Address Mapping Table
234
Figure 42: Default Host Mode Memory Map from PCI Bus Master
237
Accessing the Sibyte from Hypertransport Devices
238
Figure 43: Memory Map from Hypertransport Device
238
Force Isochronous Mode Address Range
240
Accessing the Sibyte from a Sibyte on a Double Hosted Chain
240
Hypertransport Bounce Space
241
Performance of the PCI and Hypertransport Interfaces
241
Accesses from the Sibyte to the PCI or Hypertransport
242
Figure 44: Buffers Used for Accesses from the Zbbus to PCI and Hypertransport
242
Accesses from the Hypertransport to the Sibyte
244
Figure 45: Buffers Used for DMA Accesses from the PCI and Hypertransport
244
Accesses from the PCI to the Sibyte
245
PCI Adaptive Retry
245
Figure 46: PCI Adaptive Retry Parameters
246
Table 124: Adaptive Retry Delay
246
Peer-To-Peer Accesses
247
PCI Bus to Hypertransport Fabric
247
Figure 47: Buffers Used for PCI to Hypertransport Peer-To-Peer Accesses
248
Figure 48: Buffers Used for Hypertransport to PCI Peer-To-Peer Accesses
249
PCI Arbiter
250
PCI Interrupts
250
Hypertransport Differences from Revision 1.03 Specification
252
Table 125: Error Routing Registers
257
Ordering Rules
259
Using the PCI in Device Mode
260
Table 126: PCI CSR Access Rules
261
Figure 49: Configuration Space Address
262
Hypertransport Target Done Counter
264
Systems that Do Not Use Hypertransport
264
Configuration Header Descriptions
264
PCI Configuration Header
264
Table 127: PCI Interface Configuration Header (Type 0)
264
Table 128: PCI Command Register - Offset 4 Bits [15:0]
267
Table 129: PCI Status Register - Offset 4 Bits [31:16]
267
Table 130: PCI Latency Timer - Offset 0C Bits [15:8]
268
Table 131: PCI Cache Line Size - Offset 0C Bits [7:0]
268
Table 132: PCI Timeout Register - Offset 40 Bits [15:0]
268
Table 133: PCI Feature Control Register - Offset 40 Bits [31:16]
269
Table 135: PCI Additional Status and Control Register - Offset 88 Bits [31:0]
269
Table 136: PCI INTA Control Register - Offset 90 Bits [31:0]
270
Table 137: PCI Read Host Register - Offset 94 Bits [31:0]
270
Table 138: PCI Adaptive Extend Register - Offset 98 Bits [31:0]
270
Table 139: PCI Bypass Control Register - Revid >= 3 Offset A8 Bits [31:0]
271
Table 140: Hypertransport Configuration Header (Type 1)
272
Table 141: Hypertransport Bridge Command Register - Offset 4 Bits [15:0]
274
Table 142: Hypertransport Bridge Primary (Zbbus) Status Register - Offset 4 Bits [31:16]
275
Table 143: Hypertransport Bridge Secondary (HT) Status Register - Offset 1C Bits [31:16]
275
Table 144: Hypertransport Bridge Control Register - Offset 3C Bits [31:16]
276
Table 145: Hypertransport Command Register - Offset 40 Bits [31:16]
276
Table 146: Hypertransport Link Control Register - Offset 44 Bits [15:0]
277
Table 147: Hypertransport Link Configuration Register - Offset 44 Bits [31:16]
278
Table 148: Hypertransport Link Frequency Register - Offset 48 Bits [15:8]
278
Table 149: Hypertransport SRI Command Register - Offset 50 Bits [31:16]
279
Table 150: Hypertransport Isochronous BAR - Offset 5C Bits [31:0]
279
Table 151: Hypertransport Isochronous Ignore Mask - Offset 60Bits [31:0]
280
Table 152: Hypertransport Error Control Register - Offset 68 Bits [23:0]
280
Table 153: Hypertransport Error Status Register - Offset 68 Bits [31:24]
281
Table 154: Hypertransport SRI Transmit Control Register - Offset 6C Bits [23:16]
281
Table 155: Hypertransport SRI Data Buffer Allocation Register - Offset 6C Bits [15:0]
281
Table 157: Hypertransport SRI Transmit Buffer Count Max Register - Offset C8 Bits [31:0]
282
Table 158: Hypertransport Diagnostic Receive CRC Expected - Offset DC
282
Table 159: Hypertransport Diagnostic Receive CRC Received - Offset F0
282
Figure 50: Hypertransport Interface Clocks and Fifos
283
Configuration Flags in the Sricmd Register
284
Timing Registers: Srirxden, Sritxden, Srirxnum and Sritxnum
284
Receive Pointer Margin Control in Sricmd Register
285
Transmit Pointer Initial Offset in the Sricmd Register
286
Error Control Register
286
Transmit Control Register
286
Buffer Control: Txbufcountmax and Databufalloc
287
Hypertransport Resets
287
Section 9: Ethernet Macs
291
Introduction
291
Interface Overview
292
Figure 51: Ethernet Interface Block Diagram
292
Protocol Engine and GMII/MII
294
Ethernet Frame Format
295
Figure 52: Ethernet Frame Format
295
Table 160: Ethernet Frame Fields
296
Prepended Header Frame Format
297
Figure 53: Prepended Header Format
297
Protocol Engine Configuration
298
Interface to PHY
298
Figure 54: Transmit FIFO Thresholds
299
Table 161: Transmission Error Conditions
300
Transmit Path
301
Receiver Operation
302
Receiver Configuration
302
Figure 55: Receive FIFO Thresholds
302
Table 162: Receiver Error Conditions
303
Receive Path
304
Destination Address Filtering
305
Figure 56: Receive Address Filter
305
Figure 57: Receive Channel Selection
308
Figure 58: Selecting the Channel Offset
308
Packet Type Identification
309
Table 163: Ethernet Type Mappings
309
Ipv4 Header Checksum
310
TCP Checksum Checking
310
Packets Dropped by the DMA Channel
310
Flow Control
311
Table 164: Back Pressure Methods in Half-Duplex Operation
311
Table 165: Pause Frame Options
312
Interrupts
313
Standard Interrupt Signaling
313
Management Interface to PHY
314
Figure 59: MDIO Flows
315
RMON Counters
316
Table 166: MAC to PHY Management Protocol
316
Table 167: RMON Counters
316
Packet FIFO Interfaces
319
Table 168: BCM1125 Ethernet/Fifo Pin Usage
319
Table 169: BCM1250 Ethernet/Fifo Pin Usage
320
Flow Control in Encoded Packet FIFO Modes
321
8-Bit Packet FIFO Operation
321
Figure 60: 8-Bit Packet FIFO GMII Style
322
Table 170: Codes for GMII Packet FIFO Mode
322
Figure 61: 8-Bit Packet FIFO Encoded Style
323
Table 171: Codes for 8-Bit Encoded Bypass Mode
323
Figure 62: 8-Bit Packet FIFO SOP Style
324
Table 172: Codes for 8-Bit SOP Packet FIFO
324
Figure 63: 8-Bit Packet FIFO EOP Style
325
Table 173: Codes for 8-Bit EOP Bypass Mode
325
16-Bit Packet FIFO Operation
326
Figure 64: 16-Bit GMII Style Packet FIFO
326
16-Bit Encoded Packet FIFO
327
Figure 65: 16-Bit Encoded Packet FIFO
327
Table 174: Codes for 16-Bit GMII Style Packet FIFO
327
Table 175: Codes for 16-Bit Encoded Bypass Mode
327
Restrictions When Resetting the Interface
328
MAC Registers
329
Table 176: MAC Configuration Registers
329
Table 177: MAC Enable Registers
333
Table 178: MAC Transmit DMA Control Register
333
Table 179: MAC FIFO Threshold Registers
334
Table 180: MAC Frame Configuration Registers
335
Table 181: MAC VLAN Tag Registers
337
Table 182: MAC Status Registers
337
Table 183: MAC Status 1 Register
340
Table 184: MAC Debug Status Registers
340
Table 185: MAC Interrupt Mask Registers
341
Table 186: MAC FIFO Pointer Registers
341
Table 187: MAC Receive Address Filter Exact Match Registers
341
Table 189: MAC Receive Address Filter Hash Match Registers
342
Table 190: MAC Transmit Source Address Registers
342
Table 191: MAC Packet Type Configuration Registers
343
Table 192: MAC Receive Address Filter Control Registers
343
Table 193: MAC Receive Channel Select Map Registers
345
Table 194: MAC MII Management Interface Registers
345
Section 10: Serial Interfaces
348
Introduction
348
Asynchronous Mode
348
Table 195: Serial Interface Signal Names
348
Table 196: Baud Rate Counter Values
349
Operation
350
Interrupts
352
Figure 66: UART Interrupt Generation
352
Loopback
353
DUART Registers
354
Table 197: DUART Mode Registers
354
Table 198: DUART Second Mode Registers
354
Table 199: DUART Command Registers
355
Table 200: DUART Status Registers
355
Table 201: DUART Baud Rate Clock Registers
356
Table 202: DUART Full Interrupt Control Registers
356
Table 203: DUART Received Data Registers
356
Table 204: DUART Transmit Data Registers
357
Table 205: DUART Input Port Register
357
Table 206: DUART Input Port Change Status Register
357
Table 207: DUART Debug Access Input Port Change Register
358
Table 208: DUART Input Port Change Status Register for Channel a
358
Table 209: DUART Input Port Change Status Register for Channel B
358
Table 210: DUART Output Port Control Register
358
Table 211: DUART Per Channel Output Control Registers
359
Table 212: DUART Aux Control Register
359
Table 213: DUART Per Channel Aux Control Registers
359
Table 214: DUART Interrupt Status Register
360
Table 215: DUART Channel a Only Interrupt Status Register
360
Table 216: DUART Channel B Only Interrupt Status Register
360
Table 217: DUART Interrupt Mask Register
361
Table 218: DUART Channel a Only Interrupt Mask Register
361
Table 219: DUART Channel B Only Interrupt Mask Register
361
Table 220: DUART Output Port Set Register
362
Table 221: DUART Output Port Clear Register
362
Table 222: DUART Output Port RTS Register
362
Synchronous Mode
364
Functional Overview
364
Figure 67: Synchronous Interface Block Diagram
365
Table 223: Synchronous Serial Interface Signal Names
366
Table 224: Synchronous Serial Interface GPIO Pins
366
Input Line Interface
367
Input Using an External Enable
367
Figure 68: Example Reception Using RIN as Active High Enable (Sampling on the Falling Clock Edge)
367
Input Using the Internal Sequencer
368
Table 225: Sequencer Table Entries
368
Output Line Interface
369
Output Using an External Enable
369
Figure 69: Example Reception Using RIN as Active High Sync (Sampling on the Falling Clock Edge)
369
Output Using the Internal Sequencer
370
Figure 70: Example Transmission Using TIN as Active High Enable (Driving/Sampling on Rising Clock Edge)
370
Synchronous Serial Protocol Engine
371
Figure 71: Example Transmission Using TIN as Active High Sync (Transition/Sampling on Rising Clock Edge)
371
Table 226: HDLC Frame Structure
371
Framing Parameters
372
HDLC Transmitter
372
Table 227: Option Flags for Synchronous Serial Transmit Channel
372
HDLC Receiver
374
Figure 72: Frame Address Matching
374
Operation in Transparent Mode
376
Table 228: Status Flags for Synchronous Serial Receive Channel
376
Transmitter in Transparent Mode
377
Receiver in Transparent Mode
377
Synchronous Interface Configuration
378
DMA Configuration
378
FIFO Configuration
378
Synchronous Serial Interrupts
379
Synchronous Serial Loopback
379
Figure 73: Synchronous Serial Loopback Connections
379
RMON Counters
380
Table 230: RMON Counters
380
Table 231: Serial Mode Configuration Register
381
Table 232: Synchronous Serial Clock Source and Line Interface Mode Register
381
Table 233: Synchronous Serial Command Register (Write-Only)
382
Table 234: Serial Write Threshold Register
383
Table 235: Serial Transmit Read Threshold Register
383
Table 236: Serial Receive Read Threshold Register
383
Table 237: Serial Minimum Frame Size Register
383
Table 238: Serial Maximum Frame Size Register
384
Table 239: Serial DMA Enable Registers
384
Table 240: Synchronous Serial Status Register
384
Table 241: Serial Status Debug Register
385
Table 242: Serial Interrupt Mask Register
385
Table 243: Serial Address Mask Register
386
Table 244: Serial Address Match Register
386
Table 245: Sequencer Table Entries
386
Table 246: Serial RMON Counters
387
Section 11: Generic/Boot Bus
389
Introduction
389
Overview
389
Configuring a Chip Select Region
390
Address Range
390
Table 247: Byte Lanes for the Generic Bus
390
Cacheable Access Blocking
391
Generic Bus Parity
391
Bus Width
392
Generic Bus Timing
392
Table 248: Generic Bus Timing Parameters
393
Figure 74: Fixed Cycle Read Access
394
Fixed Cycle Write Access
395
Figure 75: Fixed Cycle Write Access
395
Figure 76: Acknowledge Read Access
396
Figure 77: Acknowledge Write Access
397
Burst Mode
398
Figure 78: Generic Bus Burst Read
398
Figure 79: Generic Bus Burst Write
398
Table 249: Burst Cycle Summary
399
Early Chip Select
400
Boot ROM Support
400
Table 250: Generic Bus Configuration for each Boot Mode
400
Generic Bus Errors
401
Drive Strength Control
401
Generic Bus Registers
402
Table 251: Generic Bus Region Configuration Registers
402
Table 252: Generic Bus Region Size Registers
402
Table 253: Generic Bus Region Base Address Registers
403
Table 254: Generic Bus Region Timing 0 Registers
403
Table 255: Generic Bus Region Timing 1 Registers
404
Table 256: Generic Bus Interrupt Status Register
404
Table 260: Generic Bus Error Data Register 3
406
Table 263: Generic Bus Error Parity Register
406
Table 264: Output Drive Control Register 0
407
Table 266: Output Drive Control Register 2
408
Table 267: Output Drive Control Register 3
408
Section 12: PCMCIA Control Interface
411
Introduction
411
Connecting Apcmcia Slot
411
Direct Connection of a Memory Only Card
412
Figure 80: Example PCMCIA Slot Connection
412
Table 268: Source for PCMCIA Card Enable Signals
413
Table 269: PCMCIA 3.3V and 5V VCC Power Enable Truth Table
414
Table 270: PCMCIA VPP Power Enable Truth Table
415
Using the PCMCIA Card
417
Example PCMCIA Timings
418
Table 271: Example Flash Card AC Specs
418
Figure 81: Example Flash Card Timing Diagram
419
Using the Power Outputs
420
Table 272: Example Generic Bus Timing Parameters
420
Table 273: PCMCIA Configuration Register
421
Table 274: PCMCIA Status Register
422
Section 13: GPIO
424
Introduction
424
The GPIO Pins
424
Figure 82: Single GPIO Pin Diagram
424
Table 275: GPIO Pins and Alternate Uses
425
GPIO Registers
426
Table 276: GPIO Edge Clear Register
426
Table 277: GPIO Interrupt Type Register
426
Table 278: GPIO Read Register
426
Table 279: GPIO Input Invert Control Register
426
Table 280: GPIO Glitch Filter Select Register
427
Table 281: GPIO Direction Register
427
Table 282: GPIO Pin Clear Register
427
Table 283: GPIO Pin Set Register
427
Other Pins that Can be Used
428
Serial Ports
428
Pci
428
Macs
428
PCMCIA Power Control Pins
428
Table 284: Other Pins that Can be Used as General Inputs or Outputs
428
Section 14: Serial Configuration Interface
431
Introduction
431
Smbus Overview
431
Transport Protocol
431
Figure 83: Smbus Signaling Start, Data Transfer and Stop
432
Smbus Protocol
433
Table 285: Supported Smbus Transfer Types
433
Extended Protocol
434
Table 286: Command/Address Options
435
Table 287: Write Data Options
435
Table 288: Read Data Options
436
Using Extended Protocols
439
Direct Access
440
Booting Using an Smbus EEPROM
440
Switching from Smbus Mode
441
Smbus Registers
443
Table 289: Smbus Clock Frequency Registers
443
Table 290: Smbus Command Registers
443
Table 291: Smbus Control Registers
443
Table 292: Smbus Status Registers
444
Table 293: Smbus Data Registers
444
Table 294: Smbus Extra Data Registers
444
Table 295: Smbus Packet Error Check Registers
445
Table 296: Smbus Start and Command Registers Smbus Mode
445
Table 297: Smbus Start and Command Registers Extended Mode
446
Section 15: JTAG and Debug
449
Introduction
449
TAP Controller
449
Table 298: JTAG Signals
449
Figure 84: JTAG TAP State Machine
450
Table 299: JTAG Instructions
451
BYPASS Instruction
452
IDCODE Instruction
452
WAFERID Instruction
452
Table 300: JTAG Device ID Register
452
IMPCODE Instruction
453
ADDRESS Instruction
453
DATA Instruction
453
CONTROL Instruction
453
EJTAGALL Instruction
453
EJTAGBOOT Instruction
453
Table 301: JTAG Wafer ID Register
453
NORMALBOOT Instruction
454
SCAN Instructions (0X26 - 0X38)
454
SYSCTRL Instruction
454
Table 302: System Control Scan Chain
455
TRACE Instruction
457
PERF Instruction
457
Table 303: Performance Counter Scan Chain
457
TRACECTRL and TRACECURCNT Instructions
458
Table 304: Trace Control Scan Chain
458
Table 305: Trace Current Count Scan Chain
458
PROCESSMON Instruction
459
Boundary Scan Register
459
Table 306: Ring Oscillator Scan Chain
459
Figure 85: JTAG Boundary Scan Register Block
460
Figure 86: JTAG Hypertransport Output Boundary Scan Block
461
Figure 87: JTAG Hypertransport Input Boundary Scan Block
462
Processor and Probe Access
463
Table 307: CPU and Probe Accesses
463
Figure 88: Example JTAG Probe Flowchart
464
Processor Accesses to the JTAG Space
465
Probe Accesses to the Zbbus
465
Address Register
466
Data Register
466
Table 308: JTAG Address Register Scan Chain
466
Table 309: Data Register Scan Chain
466
EJTAG Control Register
467
Table 310: EJTAG Control Register
467
Differences from EJTAG 2.5 (Feb. 22, 2000) Specification
469
Table 311: Internal Register Addresses by Function
473
Table 312: Internal Registers Ordered by Address
491
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