Smbus Protocol; Table 285: Supported Smbus Transfer Types - Broadcom BCM1250 User Manual

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User Manual
10/21/02
T
P
RANSPORT
A system reset during an SMBus transaction can leave the bus in an unuseable state. The reset will cause the
master to release the clock line and SCL will therefore go high. But many slaves do not detect the system reset,
and if a slave is being read it is not permitted to change the state of the data line while the clock is high.
Following a reset it is possible for a slave to be driving the SDA low while SCL is high. All masters will backoff
from using the bus since it looks as though it is in use. A START or STOP cannot be sent because the slave
is forcing the SDA low.
The interface will attempt to clear this bad state. If SDA is detected low when the interface is released from
reset it will issue clock pulses on SCL until SDA goes high. In the absence of protocol errors, at most 9 clock
pulses are needed to ensure that any slave that believes a read is in progress will complete transfer of a byte
(of 0s) and see a NACK, causing it to end the transaction. If SDA goes high before the slave believes the
transaction is finished the interface will stop providing clock pulses but the bus will be left in a state where a
new master can initiate a new transaction. The START of the next transaction will ensure all slave state
machines are resynchronized to the command stream. If a genuine transcation is in progress under the control
of another master the part's attempt to clear state will at worst result in clock cycle stretching and should not
interfere with the transaction.
During the reset procedure accesses to the control registers are held off. This will at most last for the first 90us
after reset so it is unlikely to be noticed in practice.
SMB
P
US
ROTOCOL
The SMBus protocol defines a number of transfer types between the host and peripherals. The interface
implements all of these except for process call and block transfers. The latest revision of the SMBus includes
Packet Error Code (PEC) checking, this appends an 8-bit CRC (using the polynomial x
end of the message. The CRC is calculated across all bytes in the transfer (address, mode and data). The
receiver can verify correctness of the CRC and issues a Not Acknowledge if it is incorrect.
The interface allows use of PEC by optionally adding a byte at the end of a transfer, but the hardware will
neither generate nor check the PEC byte. Software should calculate the correct value to be sent with writes
and must load this into the smb_pec register before starting the transfer. If the CRC check fails at the slave
device it will NACK the PEC byte and an error will be reported in the smb_status register. When the interface
receives PEC it is always acting as the transaction master, so the hardware will always NACK the byte and
signal a stop to terminate the transfer. Software should then check the smb_pec register and can retry the
transfer if it detects an error.
The supported SMBus commands are listed in
Transfer Type
Command
(smb_tt)
(smb_cmd)
In the figures below S = start, P = stop, A = ACK, A = NACK, Wr (write) = 0, Rd (read) = 1
Quick Command
(110)
1
S Slave Address Data
Document
1250_1125-UM100CB-R
R
ROTOCOL
ESET

Table 285: Supported SMBus Transfer Types

1st Byte
(smb_data[7:0])
Bits driven by the slave are shaded
No
No
7
1
1 1
A P
B r oadco m C orp or ati on
BCM1250/BCM1125/BCM1125H
Table
285, along with the parameters they use.
2nd Byte
(smb_data[15:8]
No
Send a single bit (in the R/W bit position) to
the slave.
Section 14: Serial Configuration Interface Page
8
2
+ x
+ x + 1) at the
Description
405

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