Cpu To Cpu Communication (Bcm1250 Only); External Interrupts - Broadcom BCM1250 User Manual

User Manual
10/21/02
CPU CPU C
TO
The two CPUs in a BCM1250 can communicate and share information in several ways. The MIPS Load Linked
(ll and lld) and store conditional (sc and scd) instructions can be used to implement atomic operations. When
there is genuine sharing, the L1 cache to L1 cache latency is 28-36 CPU cycles.
Inter-processor interrupts are possible in several ways using a per-CPU mailbox register. This is described in
more detail in
to the mailbox, which directly raises the receiving CPUs interrupt line. The total latency for this is 20-30 CPU
cycles plus any context switch time needed. 7-12 of these cycles are taken between the receiving CPUs
interrupt being raised and its fetching from the exception vector. The interrupt is attached as an exception to a
convenient instruction: if the pipeline is running there will immediately be an instruction to use so the shorter
time will apply, the longer time is taken when the pipeline is stalled and the instruction that will carry the
exception has to be generated.
E I
XTERNAL NTERRUPTS
External interrupts from the PCI inputs are synchronized into the internal clock and pass through the interrupt
mapper (see
in the CPU, there is a latency of 17-22 CPU cycles plus about 2ns from the external pin being asserted to the
CPU fetching the first instruction from the exception vector. (Note that this is a guideline only, these times are
not specified or tested and may vary between parts.)
External interrupts from the GPIO pins are synchronized and filtered to remove glitches before being passed
through the interrupt mapper and to the CPU. When configured for the 60ns glitch filter there is a total latency
of 20-25 CPU cycles plus about 112ns from the external pin being asserted and the CPU fetching the first
instruction of the exception vector. (Note that this is a guideline only, these times are not specified or tested
and may vary between parts.)
Document 1250_1125-UM100CB-R
OMMUNICATION
Section: "Mailbox Registers" on page
Section: "Interrupts" on page
B r oadco m C orp or ati on
BCM1250/BCM1125/BCM1125H
(BCM1250 O
NLY
46. The generating CPU will do a write across the ZBbus
47) before raising the CPU interrupt input. Including the 7-12 cycles
)
Section 3: System Overview Page 19