Figure 19: Example 1Gb With Two Chip Selects Interleaved Across Both Channels - Broadcom BCM1250 User Manual

User Manual
10/21/02
Figure 19 shows this, with the interleave on a relatively low address bit. Notice that again the chip select ranges
are the same for both selects, but in this case they are for different channels.
FF_FFFF_FFFF
80_0000_0000
01_0000_0000
00_D000_0000
00_C000_0000
00_A000_0000
00_9000_0000
00_8000_0000
00_1000_0000
00_0000_0000

Figure 19: Example 1GB with two chip selects interleaved across both channels

These examples have benefited from the memory address space map having a contiguous 1GB range.
Additional memory could be added in the expansion space. However, there are some configurations that
require a 2GB chip select region. For example if the configurations used in
upgraded to use 1Gb memory technology (rather than 512 Mb) the size will double. The same effect will be
seen if two additional physical banks are added and 4-way chip select interleave used in the single channel
case or channel and chip select interleaving used in the dual channel case. Systems using the Big Memory
mode (see Section: "Larger Memory Systems" on page
density memory parts.
The 2GB problem can be solved with a little help from software. The hardware is configured in a way that
creates an alias of the low 1GB of memory which software should ensure is never used (for example by the
virtual-physical address translation in the TLB). Rather than creating a 2GB chip select range, the chip selects
are programmed for a 6GB range and address bits [32:31] are not selected for use as a row, column or bank
address. Thus the real 2GB range appears 3 times in the range given to the chip selects.
Document 1250_1125-UM100CB-R
HT
SDRAM Expansion
Peripherals/L2 mgmt
Fourth SDRAM
Reserved
Third SDRAM
Second SDRAM
Peripherals
First SDRAM
Physical Address
(used by CPU and DMA)
B r oadco m C orp or ati on
BCM1250/BCM1125/BCM1125H
Expansion space
direct map
This range cannot
be accessed
bank3_map
bank2_map
bank1_map
bank0_map
MC Address Space
(only used for MC configuration)
124) will also face this issue even when using lower
channel_sel=bit7
Channel 1, chip select 0
cs0_start=00_00 cs0_end=00_40
Channel 0, chip select 0
cs0_start=00_00 cs0_end=00_40
Figure 17 - Figure 19
Section 6: DRAM Page
were
115